Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Atheros AR71XX/AR724X/AR913X built-in hardware watchdog timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This driver was based on: drivers/watchdog/ixp4xx_wdt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	Author: Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Copyright 2004 (c) MontaVista, Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * which again was based on sa1100 driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *	Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DRIVER_NAME	"ath79-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WDT_TIMEOUT	15	/* seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WDOG_REG_CTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WDOG_REG_TIMER		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WDOG_CTRL_LAST_RESET	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WDOG_CTRL_ACTION_MASK	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WDOG_CTRL_ACTION_NONE	0	/* no action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WDOG_CTRL_ACTION_GPI	1	/* general purpose interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WDOG_CTRL_ACTION_NMI	2	/* NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WDOG_CTRL_ACTION_FCR	3	/* full chip reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			   "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int timeout = WDT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) module_param(timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			  "(default=" __MODULE_STRING(WDT_TIMEOUT) "s)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static unsigned long wdt_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WDT_FLAGS_BUSY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WDT_FLAGS_EXPECT_CLOSE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static struct clk *wdt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static unsigned long wdt_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int boot_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int max_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static void __iomem *wdt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static inline void ath79_wdt_wr(unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	iowrite32(val, wdt_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static inline u32 ath79_wdt_rr(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return ioread32(wdt_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline void ath79_wdt_keepalive(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ath79_wdt_wr(WDOG_REG_TIMER, wdt_freq * timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ath79_wdt_rr(WDOG_REG_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static inline void ath79_wdt_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ath79_wdt_keepalive();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * Updating the TIMER register requires a few microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * on the AR934x SoCs at least. Use a small delay to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * that the TIMER register is updated within the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * before enabling the watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ath79_wdt_rr(WDOG_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline void ath79_wdt_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ath79_wdt_rr(WDOG_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int ath79_wdt_set_timeout(int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (val < 1 || val > max_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	timeout = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ath79_wdt_keepalive();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int ath79_wdt_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ath79_wdt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return stream_open(inode, file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int ath79_wdt_release(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		ath79_wdt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		pr_crit("device closed unexpectedly, watchdog timer will not stop!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		ath79_wdt_keepalive();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	clear_bit(WDT_FLAGS_BUSY, &wdt_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static ssize_t ath79_wdt_write(struct file *file, const char *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				size_t len, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		if (!nowayout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			for (i = 0; i != len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				if (get_user(c, data + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				if (c == 'V')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 					set_bit(WDT_FLAGS_EXPECT_CLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 						&wdt_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		ath79_wdt_keepalive();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct watchdog_info ath79_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.options		= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				  WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.firmware_version	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.identity		= "ATH79 watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static long ath79_wdt_ioctl(struct file *file, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			    unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	int __user *p = argp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case WDIOC_GETSUPPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		err = copy_to_user(argp, &ath79_wdt_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				   sizeof(ath79_wdt_info)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case WDIOC_GETSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		err = put_user(0, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case WDIOC_GETBOOTSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		err = put_user(boot_status, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	case WDIOC_KEEPALIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ath79_wdt_keepalive();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case WDIOC_SETTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		err = get_user(t, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		err = ath79_wdt_set_timeout(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case WDIOC_GETTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		err = put_user(timeout, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		err = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct file_operations ath79_wdt_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.llseek		= no_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.write		= ath79_wdt_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.unlocked_ioctl	= ath79_wdt_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.compat_ioctl	= compat_ptr_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.open		= ath79_wdt_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.release	= ath79_wdt_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct miscdevice ath79_wdt_miscdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.minor = WATCHDOG_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.name = "watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.fops = &ath79_wdt_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int ath79_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (wdt_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	wdt_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (IS_ERR(wdt_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return PTR_ERR(wdt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	wdt_clk = devm_clk_get(&pdev->dev, "wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (IS_ERR(wdt_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return PTR_ERR(wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	err = clk_prepare_enable(wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	wdt_freq = clk_get_rate(wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (!wdt_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	max_timeout = (0xfffffffful / wdt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (timeout < 1 || timeout > max_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		timeout = max_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			"timeout value must be 0 < timeout < %d, using %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			max_timeout, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ctrl = ath79_wdt_rr(WDOG_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	boot_status = (ctrl & WDOG_CTRL_LAST_RESET) ? WDIOF_CARDRESET : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	err = misc_register(&ath79_wdt_miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			"unable to register misc device, err=%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	clk_disable_unprepare(wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int ath79_wdt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	misc_deregister(&ath79_wdt_miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	clk_disable_unprepare(wdt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void ath79_wdt_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ath79_wdt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct of_device_id ath79_wdt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ .compatible = "qca,ar7130-wdt" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DEVICE_TABLE(of, ath79_wdt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct platform_driver ath79_wdt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.probe		= ath79_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.remove		= ath79_wdt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.shutdown	= ath79_wdt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.name	= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.of_match_table = of_match_ptr(ath79_wdt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) module_platform_driver(ath79_wdt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X hardware watchdog driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_ALIAS("platform:" DRIVER_NAME);