Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * drivers/watchdog/at91sam9_wdt.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2007 Andrew Victor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2007 Atmel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Watchdog Timer (WDT) - System peripherals regsters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Based on AT91SAM9261 datasheet revision D.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Based on SAM9X60 datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef AT91_WDT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AT91_WDT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AT91_WDT_CR		0x00			/* Watchdog Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define  AT91_WDT_WDRSTT	BIT(0)			/* Restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define  AT91_WDT_KEY		(0xa5UL << 24)		/* KEY Password */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AT91_WDT_MR		0x04			/* Watchdog Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define  AT91_WDT_WDV		(0xfffUL << 0)		/* Counter Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define  AT91_WDT_SET_WDV(x)	((x) & AT91_WDT_WDV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define  AT91_SAM9X60_PERIODRST	BIT(4)		/* Period Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define  AT91_SAM9X60_RPTHRST	BIT(5)		/* Minimum Restart Period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define  AT91_WDT_WDFIEN	BIT(12)		/* Fault Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define  AT91_SAM9X60_WDDIS	BIT(12)		/* Watchdog Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define  AT91_WDT_WDRSTEN	BIT(13)		/* Reset Processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define  AT91_WDT_WDRPROC	BIT(14)		/* Timer Restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define  AT91_WDT_WDDIS		BIT(15)		/* Watchdog Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define  AT91_WDT_WDD		(0xfffUL << 16)		/* Delta Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define  AT91_WDT_SET_WDD(x)	(((x) << 16) & AT91_WDT_WDD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define  AT91_WDT_WDDBGHLT	BIT(28)		/* Debug Halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define  AT91_WDT_WDIDLEHLT	BIT(29)		/* Idle Halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_WDT_SR		0x08		/* Watchdog Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define  AT91_WDT_WDUNF		BIT(0)		/* Watchdog Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define  AT91_WDT_WDERR		BIT(1)		/* Watchdog Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Watchdog Timer Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT91_SAM9X60_VR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Watchdog Window Level Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AT91_SAM9X60_WLR	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Watchdog Period Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define  AT91_SAM9X60_COUNTER	(0xfffUL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define  AT91_SAM9X60_SET_COUNTER(x)	((x) & AT91_SAM9X60_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT91_SAM9X60_IER	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Period Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define  AT91_SAM9X60_PERINT	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AT91_SAM9X60_IDR	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT91_SAM9X60_ISR	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif