Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2016 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Joel Stanley <joel@jms.id.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct aspeed_wdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	struct watchdog_device	wdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u32			ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct aspeed_wdt_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32 ext_pulse_width_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const struct aspeed_wdt_config ast2400_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.ext_pulse_width_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static const struct aspeed_wdt_config ast2500_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.ext_pulse_width_mask = 0xfffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static const struct of_device_id aspeed_wdt_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{ .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WDT_STATUS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WDT_RELOAD_VALUE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WDT_RESTART		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WDT_CTRL		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define   WDT_CTRL_BOOT_SECONDARY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   WDT_CTRL_RESET_MODE_SOC	(0x00 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   WDT_CTRL_RESET_MODE_FULL_CHIP	(0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define   WDT_CTRL_RESET_MODE_ARM_CPU	(0x10 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define   WDT_CTRL_1MHZ_CLK		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define   WDT_CTRL_WDT_EXT		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define   WDT_CTRL_WDT_INTR		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define   WDT_CTRL_RESET_SYSTEM		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define   WDT_CTRL_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WDT_TIMEOUT_STATUS	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define   WDT_TIMEOUT_STATUS_BOOT_SECONDARY	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WDT_CLEAR_TIMEOUT_STATUS	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define   WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * enabled), specifically:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * * Pulse duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * * Drive mode: push-pull vs open-drain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * * Polarity: Active high or active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * Pulse duration configuration is available on both the AST2400 and AST2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * though the field changes between SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * AST2400: Bits 7:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * AST2500: Bits 19:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * This difference is captured in struct aspeed_wdt_config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * The AST2500 exposes the drive mode and polarity options, but not in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * regular fashion. For read purposes, bit 31 represents active high or low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * and bit 30 represents push-pull or open-drain. With respect to write, magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * values need to be written to the top byte to change the state of the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * mode and polarity bits. Any other value written to the top byte has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * effect on the state of the drive mode or polarity bits. However, the pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * width value must be preserved (as desired) if written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WDT_RESET_WIDTH		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define   WDT_RESET_WIDTH_ACTIVE_HIGH	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define     WDT_ACTIVE_HIGH_MAGIC	(0xA5 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define     WDT_ACTIVE_LOW_MAGIC	(0x5A << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define   WDT_RESET_WIDTH_PUSH_PULL	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define     WDT_PUSH_PULL_MAGIC		(0xA8 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define     WDT_OPEN_DRAIN_MAGIC	(0x8A << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define WDT_RESTART_MAGIC	0x4755
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* 32 bits at 1MHz, in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define WDT_MAX_TIMEOUT_MS	4294967
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define WDT_DEFAULT_TIMEOUT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define WDT_RATE_1MHZ		1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return container_of(wdd, struct aspeed_wdt, wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	wdt->ctrl |= WDT_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	writel(0, wdt->base + WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	writel(count, wdt->base + WDT_RELOAD_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	writel(wdt->ctrl, wdt->base + WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int aspeed_wdt_start(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int aspeed_wdt_stop(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	wdt->ctrl &= ~WDT_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	writel(wdt->ctrl, wdt->base + WDT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int aspeed_wdt_ping(struct watchdog_device *wdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				  unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32 actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	wdd->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int aspeed_wdt_restart(struct watchdog_device *wdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			      unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static ssize_t access_cs0_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			       struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct aspeed_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		      !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static ssize_t access_cs0_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct aspeed_wdt *wdt = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (kstrtoul(buf, 10, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		       wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * This attribute exists only if the system has booted from the alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * flash with 'alt-boot' option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * At alternate flash the 'access_cs0' sysfs node provides:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *   ast2400: a way to get access to the primary SPI flash chip at CS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *            after booting from the alternate chip at CS1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  *   ast2500: a way to restore the normal address mapping from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  *            (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * Clearing the boot code selection and timeout counter also resets to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * initial state the chip select line mapping. When the SoC is in normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * mapping state (i.e. booted from CS0), clearing those bits does nothing for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * both versions of the SoC. For alternate boot mode (booted from CS1 due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * wdt2 expiration) the behavior differs as described above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * This option can be used with wdt2 (watchdog1) only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static DEVICE_ATTR_RW(access_cs0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct attribute *bswitch_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	&dev_attr_access_cs0.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ATTRIBUTE_GROUPS(bswitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct watchdog_ops aspeed_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.start		= aspeed_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.stop		= aspeed_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.ping		= aspeed_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.set_timeout	= aspeed_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.restart	= aspeed_wdt_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct watchdog_info aspeed_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.options	= WDIOF_KEEPALIVEPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			| WDIOF_MAGICCLOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			| WDIOF_SETTIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.identity	= KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int aspeed_wdt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	const struct aspeed_wdt_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	const struct of_device_id *ofdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct aspeed_wdt *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	const char *reset_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u32 duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	wdt->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (IS_ERR(wdt->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return PTR_ERR(wdt->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	wdt->wdd.info = &aspeed_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	wdt->wdd.ops = &aspeed_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	wdt->wdd.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	watchdog_init_timeout(&wdt->wdd, 0, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ofdid = of_match_node(aspeed_wdt_of_table, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!ofdid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	config = ofdid->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * On clock rates:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 *  - ast2400 wdt can run at PCLK, or 1MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 *  - ast2500 only runs at 1MHz, hard coding bit 4 to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 *  - ast2600 always runs at 1MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * Set the ast2400 to run at 1MHz as it simplifies the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		wdt->ctrl = WDT_CTRL_1MHZ_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * Control reset on a per-device basis to ensure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * host is not affected by a BMC reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (!strcmp(reset_type, "cpu"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				     WDT_CTRL_RESET_SYSTEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		else if (!strcmp(reset_type, "soc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				     WDT_CTRL_RESET_SYSTEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		else if (!strcmp(reset_type, "system"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				     WDT_CTRL_RESET_SYSTEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		else if (strcmp(reset_type, "none"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (of_property_read_bool(np, "aspeed,external-signal"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		wdt->ctrl |= WDT_CTRL_WDT_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (of_property_read_bool(np, "aspeed,alt-boot"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		 * The watchdog is running, but invoke aspeed_wdt_start() to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		 * configuration conforms to the driver's expectations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		 * Primarily, ensure we're using the 1MHz clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		aspeed_wdt_start(&wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		(of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		reg &= config->ext_pulse_width_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (of_property_read_bool(np, "aspeed,ext-push-pull"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			reg |= WDT_PUSH_PULL_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			reg |= WDT_OPEN_DRAIN_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		writel(reg, wdt->base + WDT_RESET_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		reg &= config->ext_pulse_width_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (of_property_read_bool(np, "aspeed,ext-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			reg |= WDT_ACTIVE_HIGH_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			reg |= WDT_ACTIVE_LOW_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		writel(reg, wdt->base + WDT_RESET_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		u32 max_duration = config->ext_pulse_width_mask + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		if (duration == 0 || duration > max_duration) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			dev_err(dev, "Invalid pulse duration: %uus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			duration = max(1U, min(max_duration, duration));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			dev_info(dev, "Pulse duration set to %uus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				 duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		 * The watchdog is always configured with a 1MHz source, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		 * there is no need to scale the microsecond value. However we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		 * need to offset it - from the datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		 * "This register decides the asserting duration of wdt_ext and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		 * wdt_rstarm signal. The default value is 0xFF. It means the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		 * default asserting duration of wdt_ext and wdt_rstarm is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		 * 256us."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		 * This implies a value of 0 gives a 1us pulse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	status = readl(wdt->base + WDT_TIMEOUT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		wdt->wdd.bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		    of_device_is_compatible(np, "aspeed,ast2500-wdt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			wdt->wdd.groups = bswitch_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	dev_set_drvdata(dev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return devm_watchdog_register_device(dev, &wdt->wdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct platform_driver aspeed_watchdog_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.probe = aspeed_wdt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		.of_match_table = of_match_ptr(aspeed_wdt_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int __init aspeed_wdt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return platform_driver_register(&aspeed_watchdog_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) arch_initcall(aspeed_wdt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void __exit aspeed_wdt_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	platform_driver_unregister(&aspeed_watchdog_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) module_exit(aspeed_wdt_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DESCRIPTION("Aspeed Watchdog Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_LICENSE("GPL");