^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2004 Evgeniy Polyakov <zbr@ioremap.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "w1_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static int w1_delay_parm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) module_param_named(delay_coef, w1_delay_parm, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int w1_disable_irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) module_param_named(disable_irqs, w1_disable_irqs, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static u8 w1_crc8_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void w1_delay(unsigned long tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) udelay(tm * w1_delay_parm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void w1_write_bit(struct w1_master *dev, int bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static u8 w1_read_bit(struct w1_master *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @bit: 0 - write a 0, 1 - write a 0 read the level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 w1_touch_bit(struct w1_master *dev, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (dev->bus_master->touch_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return dev->bus_master->touch_bit(dev->bus_master->data, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else if (bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return w1_read_bit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) w1_write_bit(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXPORT_SYMBOL_GPL(w1_touch_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * w1_write_bit() - Generates a write-0 or write-1 cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @bit: bit to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Only call if dev->bus_master->touch_bit is NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void w1_write_bit(struct w1_master *dev, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if(w1_disable_irqs) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev->bus_master->write_bit(dev->bus_master->data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) w1_delay(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev->bus_master->write_bit(dev->bus_master->data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) w1_delay(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev->bus_master->write_bit(dev->bus_master->data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) w1_delay(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev->bus_master->write_bit(dev->bus_master->data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) w1_delay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if(w1_disable_irqs) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * w1_pre_write() - pre-write operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Pre-write operation, currently only supporting strong pullups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Program the hardware for a strong pullup, if one has been requested and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * the hardware supports it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void w1_pre_write(struct w1_master *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (dev->pullup_duration &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev->enable_pullup && dev->bus_master->set_pullup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev->bus_master->set_pullup(dev->bus_master->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev->pullup_duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * w1_post_write() - post-write options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Post-write operation, currently only supporting strong pullups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * If a strong pullup was requested, clear it if the hardware supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * them, or execute the delay otherwise, in either case clear the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void w1_post_write(struct w1_master *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (dev->pullup_duration) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (dev->enable_pullup && dev->bus_master->set_pullup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev->bus_master->set_pullup(dev->bus_master->data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) msleep(dev->pullup_duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev->pullup_duration = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * w1_write_8() - Writes 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @byte: the byte to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void w1_write_8(struct w1_master *dev, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (dev->bus_master->write_byte) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) w1_pre_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev->bus_master->write_byte(dev->bus_master->data, byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < 8; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (i == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) w1_pre_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) w1_touch_bit(dev, (byte >> i) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) w1_post_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EXPORT_SYMBOL_GPL(w1_write_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * w1_read_bit() - Generates a write-1 cycle and samples the level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Only call if dev->bus_master->touch_bit is NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static u8 w1_read_bit(struct w1_master *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* sample timing is critical here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev->bus_master->write_bit(dev->bus_master->data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) w1_delay(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev->bus_master->write_bit(dev->bus_master->data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) w1_delay(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) result = dev->bus_master->read_bit(dev->bus_master->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) w1_delay(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return result & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * w1_triplet() - * Does a triplet - used for searching ROM addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @bdir: the bit to write if both id_bit and comp_bit are 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Return bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * bit 0 = id_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * bit 1 = comp_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * bit 2 = dir_taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * If both bits 0 & 1 are set, the search should be restarted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Return: bit fields - see above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 w1_triplet(struct w1_master *dev, int bdir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (dev->bus_master->triplet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return dev->bus_master->triplet(dev->bus_master->data, bdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 id_bit = w1_touch_bit(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 comp_bit = w1_touch_bit(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (id_bit && comp_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0x03; /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!id_bit && !comp_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Both bits are valid, take the direction given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) retval = bdir ? 0x04 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Only one bit is valid, take that direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bdir = id_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) retval = id_bit ? 0x05 : 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (dev->bus_master->touch_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) w1_touch_bit(dev, bdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) w1_write_bit(dev, bdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) EXPORT_SYMBOL_GPL(w1_triplet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * w1_read_8() - Reads 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Return: the byte read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 w1_read_8(struct w1_master *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (dev->bus_master->read_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) res = dev->bus_master->read_byte(dev->bus_master->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) res |= (w1_touch_bit(dev,1) << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) EXPORT_SYMBOL_GPL(w1_read_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * w1_write_block() - Writes a series of bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @buf: pointer to the data to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @len: the number of bytes to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (dev->bus_master->write_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) w1_pre_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev->bus_master->write_block(dev->bus_master->data, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < len; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) w1_write_8(dev, buf[i]); /* calls w1_pre_write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) w1_post_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EXPORT_SYMBOL_GPL(w1_write_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * w1_touch_block() - Touches a series of bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @buf: pointer to the data to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @len: the number of bytes to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void w1_touch_block(struct w1_master *dev, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (i = 0; i < len; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) for (j = 0; j < 8; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (j == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) w1_pre_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) buf[i] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EXPORT_SYMBOL_GPL(w1_touch_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * w1_read_block() - Reads a series of bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @buf: pointer to the buffer to fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @len: the number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Return: the number of bytes read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (dev->bus_master->read_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < len; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) buf[i] = w1_read_8(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) EXPORT_SYMBOL_GPL(w1_read_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * w1_reset_bus() - Issues a reset bus sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Return: 0=Device present, 1=No device present or error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int w1_reset_bus(struct w1_master *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if(w1_disable_irqs) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (dev->bus_master->reset_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev->bus_master->write_bit(dev->bus_master->data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* minimum 480, max ? us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * be nice and sleep, except 18b20 spec lists 960us maximum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * so until we can sleep with microsecond accuracy, spin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Feel free to come up with some other way to give up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * cpu for such a short amount of time AND get it back in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * the maximum amount of time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) w1_delay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev->bus_master->write_bit(dev->bus_master->data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) w1_delay(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* minimum 70 (above) + 430 = 500 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * There aren't any timing requirements between a reset and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * the following transactions. Sleeping is safe here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* w1_delay(430); min required time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if(w1_disable_irqs) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EXPORT_SYMBOL_GPL(w1_reset_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 w1_calc_crc8(u8 * data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 crc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) crc = w1_crc8_table[crc ^ *data++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EXPORT_SYMBOL_GPL(w1_calc_crc8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev->attempts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (dev->bus_master->search)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev->bus_master->search(dev->bus_master->data, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) search_type, cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) w1_search(dev, search_type, cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * w1_reset_select_slave() - reset and select a slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @sl: the slave to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Resets the bus and then selects the slave by sending either a skip rom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * or a rom match. A skip rom is issued if there is only one device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * registered on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * The w1 master lock must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Return: 0=success, anything else=error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int w1_reset_select_slave(struct w1_slave *sl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (w1_reset_bus(sl->master))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (sl->master->slave_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) w1_write_8(sl->master, W1_SKIP_ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 match[9] = {W1_MATCH_ROM, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) memcpy(&match[1], &rn, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) w1_write_block(sl->master, match, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EXPORT_SYMBOL_GPL(w1_reset_select_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * w1_reset_resume_command() - resume instead of another match ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * When the workflow with a slave amongst many requires several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * successive commands a reset between each, this function is similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * to doing a reset then a match ROM for the last matched ROM. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * advantage being that the matched ROM step is skipped in favor of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * resume command. The slave must support the command of course.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * If the bus has only one slave, traditionnaly the match ROM is skipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * doesn't work of course, but the resume command is the next best thing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * The w1 master lock must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int w1_reset_resume_command(struct w1_master *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (w1_reset_bus(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) w1_write_8(dev, dev->slave_count > 1 ? W1_RESUME_CMD : W1_SKIP_ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) EXPORT_SYMBOL_GPL(w1_reset_resume_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * w1_next_pullup() - register for a strong pullup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * @dev: the master device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @delay: time in milliseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Put out a strong pull-up of the specified duration after the next write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * operation. Not all hardware supports strong pullups. Hardware that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * doesn't support strong pullups will sleep for the given time after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * write operation without a strong pullup. This is a one shot request for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * the next write, specifying zero will clear a previous request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * The w1 master lock must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Return: 0=success, anything else=error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) void w1_next_pullup(struct w1_master *dev, int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev->pullup_duration = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) EXPORT_SYMBOL_GPL(w1_next_pullup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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