^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * w1_ds28e17.c - w1 family 19 (DS28E17) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Jan Kandziora <jjj@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/crc16.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CRC16_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/w1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define W1_FAMILY_DS28E17 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Module setup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_AUTHOR("Jan Kandziora <jjj@gmx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_DESCRIPTION("w1 family 19 driver for DS28E17, 1-wire to I2C master bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_ALIAS("w1-family-" __stringify(W1_FAMILY_DS28E17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Default I2C speed to be set when a DS28E17 is detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int i2c_speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) module_param_named(speed, i2c_speed, int, (S_IRUSR | S_IWUSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(speed, "Default I2C speed to be set when a DS28E17 is detected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Default I2C stretch value to be set when a DS28E17 is detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static char i2c_stretch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) module_param_named(stretch, i2c_stretch, byte, (S_IRUSR | S_IWUSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_PARM_DESC(stretch, "Default I2C stretch value to be set when a DS28E17 is detected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* DS28E17 device command codes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define W1_F19_WRITE_DATA_WITH_STOP 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define W1_F19_WRITE_DATA_NO_STOP 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define W1_F19_WRITE_DATA_ONLY 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define W1_F19_WRITE_DATA_ONLY_WITH_STOP 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define W1_F19_READ_DATA_WITH_STOP 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define W1_F19_WRITE_READ_DATA_WITH_STOP 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define W1_F19_WRITE_CONFIGURATION 0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define W1_F19_READ_CONFIGURATION 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define W1_F19_ENABLE_SLEEP_MODE 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define W1_F19_READ_DEVICE_REVISION 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* DS28E17 status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define W1_F19_STATUS_CRC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define W1_F19_STATUS_ADDRESS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define W1_F19_STATUS_START 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Maximum number of I2C bytes to transfer within one CRC16 protected onewire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define W1_F19_WRITE_DATA_LIMIT 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Maximum number of I2C bytes to read with one onewire command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define W1_F19_READ_DATA_LIMIT 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Constants for calculating the busy sleep. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define W1_F19_BUSY_TIMEBASES { 90, 23, 10 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define W1_F19_BUSY_GRATUITY 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Number of checks for the busy flag before timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define W1_F19_BUSY_CHECKS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Slave specific data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct w1_f19_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Wait a while until the busy flag clears. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int w1_f19_i2c_busy_wait(struct w1_slave *sl, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const unsigned long timebases[3] = W1_F19_BUSY_TIMEBASES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct w1_f19_data *data = sl->family_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int checks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Check the busy flag first in any case.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (w1_touch_bit(sl->master, 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Do a generously long sleep in the beginning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * as we have to wait at least this time for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * the I2C bytes at the given speed to be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) usleep_range(timebases[data->speed] * (data->stretch) * count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) timebases[data->speed] * (data->stretch) * count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) + W1_F19_BUSY_GRATUITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Now continusly check the busy flag sent by the DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) checks = W1_F19_BUSY_CHECKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) while ((checks--) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Return success if the busy flag is cleared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (w1_touch_bit(sl->master, 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Wait one non-streched byte timeslot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) udelay(timebases[data->speed]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_warn(&sl->dev, "busy timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Utility function: result. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static size_t w1_f19_error(struct w1_slave *sl, u8 w1_buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Warnings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (w1_buf[0] & W1_F19_STATUS_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_warn(&sl->dev, "crc16 mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (w1_buf[0] & W1_F19_STATUS_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_warn(&sl->dev, "i2c device not responding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if ((w1_buf[0] & (W1_F19_STATUS_CRC | W1_F19_STATUS_ADDRESS)) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) && w1_buf[1] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_warn(&sl->dev, "i2c short write, %d bytes not acknowledged\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) w1_buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Check error conditions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (w1_buf[0] & W1_F19_STATUS_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (w1_buf[0] & W1_F19_STATUS_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (w1_buf[0] != 0 || w1_buf[1] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* All ok. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Utility function: write data to I2C slave, single chunk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int __w1_f19_i2c_write(struct w1_slave *sl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const u8 *command, size_t command_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const u8 *buffer, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 w1_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Send command and I2C data to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) crc = crc16(CRC16_INIT, command, command_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) w1_write_block(sl->master, command, command_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) w1_buf[0] = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) crc = crc16(crc, w1_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) w1_write_8(sl->master, w1_buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) crc = crc16(crc, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) w1_write_block(sl->master, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) w1_buf[0] = ~(crc & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) w1_buf[1] = ~((crc >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) w1_write_block(sl->master, w1_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Wait until busy flag clears (or timeout). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (w1_f19_i2c_busy_wait(sl, count + 1) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Read status from DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) w1_read_block(sl->master, w1_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Check error conditions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) error = w1_f19_error(sl, w1_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Return number of bytes written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Write data to I2C slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int w1_f19_i2c_write(struct w1_slave *sl, u16 i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const u8 *buffer, size_t count, bool stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int remaining = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 command[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Check input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Check whether we need multiple commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (count <= W1_F19_WRITE_DATA_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Small data amount. Data can be sent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * a single onewire command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Send all data to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) command[0] = (stop ? W1_F19_WRITE_DATA_WITH_STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) : W1_F19_WRITE_DATA_NO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) command[1] = i2c_address << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) result = __w1_f19_i2c_write(sl, command, 2, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Large data amount. Data has to be sent in multiple chunks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Send first chunk to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) p = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) command[0] = W1_F19_WRITE_DATA_NO_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) command[1] = i2c_address << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) result = __w1_f19_i2c_write(sl, command, 2, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) W1_F19_WRITE_DATA_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Resume to same DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (w1_reset_resume_command(sl->master))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Next data chunk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) p += W1_F19_WRITE_DATA_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) remaining -= W1_F19_WRITE_DATA_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) while (remaining > W1_F19_WRITE_DATA_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Send intermediate chunk to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) command[0] = W1_F19_WRITE_DATA_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) result = __w1_f19_i2c_write(sl, command, 1, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) W1_F19_WRITE_DATA_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Resume to same DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (w1_reset_resume_command(sl->master))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Next data chunk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) p += W1_F19_WRITE_DATA_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) remaining -= W1_F19_WRITE_DATA_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Send final chunk to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) command[0] = (stop ? W1_F19_WRITE_DATA_ONLY_WITH_STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) : W1_F19_WRITE_DATA_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) result = __w1_f19_i2c_write(sl, command, 1, p, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Read data from I2C slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int w1_f19_i2c_read(struct w1_slave *sl, u16 i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 *buffer, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 w1_buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Check input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Send command to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) w1_buf[0] = W1_F19_READ_DATA_WITH_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) w1_buf[1] = i2c_address << 1 | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) w1_buf[2] = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) crc = crc16(CRC16_INIT, w1_buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) w1_buf[3] = ~(crc & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) w1_buf[4] = ~((crc >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) w1_write_block(sl->master, w1_buf, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Wait until busy flag clears (or timeout). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (w1_f19_i2c_busy_wait(sl, count + 1) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Read status from DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) w1_buf[0] = w1_read_8(sl->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) w1_buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Check error conditions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) error = w1_f19_error(sl, w1_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Read received I2C data from DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return w1_read_block(sl->master, buffer, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Write to, then read data from I2C slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int w1_f19_i2c_write_read(struct w1_slave *sl, u16 i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const u8 *wbuffer, size_t wcount, u8 *rbuffer, size_t rcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 w1_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Check input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (wcount == 0 || rcount == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Send command and I2C data to DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) w1_buf[0] = W1_F19_WRITE_READ_DATA_WITH_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) w1_buf[1] = i2c_address << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) w1_buf[2] = wcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) crc = crc16(CRC16_INIT, w1_buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) w1_write_block(sl->master, w1_buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) crc = crc16(crc, wbuffer, wcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) w1_write_block(sl->master, wbuffer, wcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) w1_buf[0] = rcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) crc = crc16(crc, w1_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) w1_buf[1] = ~(crc & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) w1_buf[2] = ~((crc >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) w1_write_block(sl->master, w1_buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Wait until busy flag clears (or timeout). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (w1_f19_i2c_busy_wait(sl, wcount + rcount + 2) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Read status from DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) w1_read_block(sl->master, w1_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Check error conditions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) error = w1_f19_error(sl, w1_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Read received I2C data from DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return w1_read_block(sl->master, rbuffer, rcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Do an I2C master transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int w1_f19_i2c_master_transfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct w1_slave *sl = (struct w1_slave *) adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Start onewire transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_lock(&sl->master->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Select DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (w1_reset_select_slave(sl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) i = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Loop while there are still messages to transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) while (i < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Check for special case: Small write followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * by read to same I2C device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (i < (num-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) && msgs[i].addr == msgs[i+1].addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) && !(msgs[i].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) && (msgs[i+1].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) && (msgs[i].len <= W1_F19_WRITE_DATA_LIMIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * The DS28E17 has a combined transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * for small write+read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) result = w1_f19_i2c_write_read(sl, msgs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) msgs[i].buf, msgs[i].len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) msgs[i+1].buf, msgs[i+1].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) i = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Check if we should interpret the read data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * as a length byte. The DS28E17 unfortunately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * has no read without stop, so we can just do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * another simple read in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (msgs[i+1].flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) result = w1_f19_i2c_read(sl, msgs[i+1].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &(msgs[i+1].buf[1]), msgs[i+1].buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) i = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Eat up read message, too. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Read transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) result = w1_f19_i2c_read(sl, msgs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msgs[i].buf, msgs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) i = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Check if we should interpret the read data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * as a length byte. The DS28E17 unfortunately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * has no read without stop, so we can just do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * another simple read in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (msgs[i].flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) result = w1_f19_i2c_read(sl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) msgs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &(msgs[i].buf[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) msgs[i].buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) i = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Write transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Stop condition only for last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) result = w1_f19_i2c_write(sl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msgs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msgs[i].buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msgs[i].len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) i == (num-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) i = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Next message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Are there still messages to send/receive? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (i < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Yes. Resume to same DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (w1_reset_resume_command(sl->master)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) i = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* End onewire transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_unlock(&sl->master->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Return number of messages processed or error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Get I2C adapter functionality. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static u32 w1_f19_i2c_functionality(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Plain I2C functions only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * SMBus is emulated by the kernel's I2C layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * No "I2C_FUNC_SMBUS_QUICK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * No "I2C_FUNC_SMBUS_READ_BLOCK_DATA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * No "I2C_FUNC_SMBUS_BLOCK_PROC_CALL"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) I2C_FUNC_SMBUS_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) I2C_FUNC_SMBUS_WRITE_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) I2C_FUNC_SMBUS_I2C_BLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) I2C_FUNC_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* I2C adapter quirks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct i2c_adapter_quirks w1_f19_i2c_adapter_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .max_read_len = W1_F19_READ_DATA_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* I2C algorithm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const struct i2c_algorithm w1_f19_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .master_xfer = w1_f19_i2c_master_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .functionality = w1_f19_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Read I2C speed from DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int w1_f19_get_i2c_speed(struct w1_slave *sl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct w1_f19_data *data = sl->family_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Start onewire transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mutex_lock(&sl->master->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Select slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (w1_reset_select_slave(sl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Read slave configuration byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) w1_write_8(sl->master, W1_F19_READ_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) result = w1_read_8(sl->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (result < 0 || result > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Update speed in slave specific data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) data->speed = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* End onewire transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mutex_unlock(&sl->master->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Set I2C speed on DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int __w1_f19_set_i2c_speed(struct w1_slave *sl, u8 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct w1_f19_data *data = sl->family_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const int i2c_speeds[3] = { 100, 400, 900 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u8 w1_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Select slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (w1_reset_select_slave(sl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) w1_buf[0] = W1_F19_WRITE_CONFIGURATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) w1_buf[1] = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) w1_write_block(sl->master, w1_buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Update speed in slave specific data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) data->speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_info(&sl->dev, "i2c speed set to %d kBaud\n", i2c_speeds[speed]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int w1_f19_set_i2c_speed(struct w1_slave *sl, u8 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Start onewire transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_lock(&sl->master->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Set I2C speed on DS28E17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) result = __w1_f19_set_i2c_speed(sl, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* End onewire transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_unlock(&sl->master->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Sysfs attributes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* I2C speed attribute for a single chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static ssize_t speed_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct w1_slave *sl = dev_to_w1_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Read current speed from slave. Updates data->speed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) result = w1_f19_get_i2c_speed(sl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Return current speed value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return sprintf(buf, "%d\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static ssize_t speed_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct w1_slave *sl = dev_to_w1_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Valid values are: "100", "400", "900" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (count < 3 || count > 4 || !buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (count == 4 && buf[3] != '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (buf[1] != '0' || buf[2] != '0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Set speed on slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) switch (buf[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case '1':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) error = w1_f19_set_i2c_speed(sl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case '4':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) error = w1_f19_set_i2c_speed(sl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case '9':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) error = w1_f19_set_i2c_speed(sl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Return bytes written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static DEVICE_ATTR_RW(speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Busy stretch attribute for a single chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static ssize_t stretch_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct w1_slave *sl = dev_to_w1_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct w1_f19_data *data = sl->family_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Return current stretch value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return sprintf(buf, "%d\n", data->stretch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static ssize_t stretch_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct w1_slave *sl = dev_to_w1_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct w1_f19_data *data = sl->family_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Valid values are '1' to '9' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (count < 1 || count > 2 || !buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (count == 2 && buf[1] != '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (buf[0] < '1' || buf[0] > '9')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Set busy stretch value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) data->stretch = buf[0] & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Return bytes written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static DEVICE_ATTR_RW(stretch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* All attributes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct attribute *w1_f19_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &dev_attr_speed.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) &dev_attr_stretch.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct attribute_group w1_f19_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .attrs = w1_f19_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct attribute_group *w1_f19_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) &w1_f19_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Slave add and remove functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int w1_f19_add_slave(struct w1_slave *sl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct w1_f19_data *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Allocate memory for slave specific data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) data = devm_kzalloc(&sl->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) sl->family_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Setup default I2C speed on slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch (i2c_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __w1_f19_set_i2c_speed(sl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case 400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) __w1_f19_set_i2c_speed(sl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case 900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) __w1_f19_set_i2c_speed(sl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * A i2c_speed module parameter of anything else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * than 100, 400, 900 means not to touch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * speed of the DS28E17.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * We assume 400kBaud, the power-on value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) data->speed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * Setup default busy stretch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * configuration for the DS28E17.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) data->stretch = i2c_stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Setup I2C adapter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) data->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) data->adapter.algo = &w1_f19_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) data->adapter.algo_data = sl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) strcpy(data->adapter.name, "w1-");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) strcat(data->adapter.name, sl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) data->adapter.dev.parent = &sl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) data->adapter.quirks = &w1_f19_i2c_adapter_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return i2c_add_adapter(&data->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void w1_f19_remove_slave(struct w1_slave *sl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct w1_f19_data *family_data = sl->family_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Delete I2C adapter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) i2c_del_adapter(&family_data->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Free slave specific data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) devm_kfree(&sl->dev, family_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) sl->family_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Declarations within the w1 subsystem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const struct w1_family_ops w1_f19_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .add_slave = w1_f19_add_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .remove_slave = w1_f19_remove_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .groups = w1_f19_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static struct w1_family w1_family_19 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .fid = W1_FAMILY_DS28E17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .fops = &w1_f19_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Module init and remove functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int __init w1_f19_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return w1_register_family(&w1_family_19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static void __exit w1_f19_fini(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) w1_unregister_family(&w1_family_19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) module_init(w1_f19_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) module_exit(w1_f19_fini);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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