^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 1-Wire implementation for the ds2780 chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Renata Sayakhova <renata@oktetlabs.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on w1-ds2760 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _W1_DS2781_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _W1_DS2781_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Function commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define W1_DS2781_READ_DATA 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define W1_DS2781_WRITE_DATA 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define W1_DS2781_COPY_DATA 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define W1_DS2781_RECALL_DATA 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define W1_DS2781_LOCK 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Register 0x00 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DS2781_STATUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DS2781_RAAC_MSB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DS2781_RAAC_LSB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DS2781_RSAC_MSB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DS2781_RSAC_LSB 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DS2781_RARC 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DS2781_RSRC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DS2781_IAVG_MSB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DS2781_IAVG_LSB 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS2781_TEMP_MSB 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DS2781_TEMP_LSB 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS2781_VOLT_MSB 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DS2781_VOLT_LSB 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DS2781_CURRENT_MSB 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DS2781_CURRENT_LSB 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DS2781_ACR_MSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DS2781_ACR_LSB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DS2781_ACRL_MSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS2781_ACRL_LSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DS2781_AS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DS2781_SFR 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DS2781_FULL_MSB 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DS2781_FULL_LSB 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DS2781_AE_MSB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DS2781_AE_LSB 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DS2781_SE_MSB 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DS2781_SE_LSB 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Register 0x1C - 0x1E Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DS2781_EEPROM 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DS2781_EEPROM_BLOCK0_START 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Register 0x20 - 0x2F User EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DS2781_EEPROM_BLOCK0_END 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Register 0x30 - 0x5F Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DS2781_EEPROM_BLOCK1_START 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DS2781_CONTROL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DS2781_AB 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DS2781_AC_MSB 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DS2781_AC_LSB 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS2781_VCHG 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DS2781_IMIN 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DS2781_VAE 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DS2781_IAE 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DS2781_AE_40 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DS2781_RSNSP 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DS2781_FULL_40_MSB 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DS2781_FULL_40_LSB 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DS2781_FULL_4_SLOPE 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DS2781_FULL_3_SLOPE 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DS2781_FULL_2_SLOPE 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DS2781_FULL_1_SLOPE 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DS2781_AE_4_SLOPE 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DS2781_AE_3_SLOPE 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DS2781_AE_2_SLOPE 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DS2781_AE_1_SLOPE 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DS2781_SE_4_SLOPE 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DS2781_SE_3_SLOPE 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DS2781_SE_2_SLOPE 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DS2781_SE_1_SLOPE 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DS2781_RSGAIN_MSB 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DS2781_RSGAIN_LSB 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DS2781_RSTC 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DS2781_COB 0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DS2781_TBP34 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DS2781_TBP23 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DS2781_TBP12 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DS2781_EEPROM_BLOCK1_END 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Register 0x7D - 0xFF Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DS2781_FSGAIN_MSB 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DS2781_FSGAIN_LSB 0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Number of valid register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DS2781_DATA_SIZE 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DS2781_STATUS_CHGTF (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DS2781_STATUS_AEF (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DS2781_STATUS_SEF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DS2781_STATUS_LEARNF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Bit 3 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DS2781_STATUS_UVF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DS2781_STATUS_PORF (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Bit 0 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Bit 7 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DS2781_CONTROL_NBEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DS2781_CONTROL_UVEN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DS2781_CONTROL_PMOD (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DS2781_CONTROL_RNAOP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DS1781_CONTROL_UVTH (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Bit 0 - 2 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Special feature register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Bit 1 - 7 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DS2781_SFR_PIOSC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* EEPROM register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DS2781_EEPROM_EEC (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DS2781_EEPROM_LOCK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Bit 2 - 6 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DS2781_EEPROM_BL1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DS2781_EEPROM_BL0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern int w1_ds2781_io(struct device *dev, char *buf, int addr, size_t count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern int w1_ds2781_eeprom_cmd(struct device *dev, int addr, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif /* !_W1_DS2781_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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