^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Luotao Fu, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/w1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MXC W1 Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MXC_W1_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define MXC_W1_CONTROL_RDST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) # define MXC_W1_CONTROL_PST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define MXC_W1_CONTROL_RPP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MXC_W1_TIME_DIVIDER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MXC_W1_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # define MXC_W1_RESET_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mxc_w1_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct w1_bus_master bus_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * this is the low level routine to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * reset the device on the One Wire interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * on the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static u8 mxc_w1_ds2_reset_bus(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mxc_w1_device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Wait for reset sequence 511+512us, use 1500us for sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) timeout = ktime_add_us(ktime_get(), 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) udelay(511 + 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PST bit is valid after the RPP bit is self-cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (!(ctrl & MXC_W1_CONTROL_RPP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return !(ctrl & MXC_W1_CONTROL_PST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) } while (ktime_before(ktime_get(), timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * this is the low level routine to read/write a bit on the One Wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * interface on the hardware. It does write 0 if parameter bit is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * to 0, otherwise a write 1/read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct mxc_w1_device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Wait for read/write bit (60us, Max 120us), use 200us for sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) timeout = ktime_add_us(ktime_get(), 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) udelay(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* RDST bit is valid after the WR1/RD bit is self-cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return !!(ctrl & MXC_W1_CONTROL_RDST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } while (ktime_before(ktime_get(), timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int mxc_w1_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct mxc_w1_device *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mdev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (IS_ERR(mdev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return PTR_ERR(mdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) err = clk_prepare_enable(mdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clkrate = clk_get_rate(mdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (clkrate < 10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "Low clock frequency causes improper function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clkrate /= clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if ((clkrate < 980000) || (clkrate > 1020000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "Incorrect time base frequency %lu Hz\n", clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mdev->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (IS_ERR(mdev->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = PTR_ERR(mdev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Software reset 1-Wire module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writeb(0, mdev->regs + MXC_W1_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mdev->bus_master.data = mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) platform_set_drvdata(pdev, mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) err = w1_add_master_device(&mdev->bus_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) out_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_disable_unprepare(mdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * disassociate the w1 device from the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int mxc_w1_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) w1_remove_master_device(&mdev->bus_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_disable_unprepare(mdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct of_device_id mxc_w1_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .compatible = "fsl,imx21-owire" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct platform_driver mxc_w1_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "mxc_w1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .of_match_table = mxc_w1_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .probe = mxc_w1_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .remove = mxc_w1_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) module_platform_driver(mxc_w1_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_AUTHOR("Freescale Semiconductors Inc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_DESCRIPTION("Driver for One-Wire on MXC");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags