^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * matrox_w1.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2004 Evgeniy Polyakov <zbr@ioremap.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/w1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Matrox G400 DDC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MATROX_G400_DDC_CLK (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MATROX_G400_DDC_DATA (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MATROX_BASE 0x3C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MATROX_STATUS 0x1e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MATROX_PORT_INDEX_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MATROX_PORT_DATA_OFFSET 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MATROX_GET_CONTROL 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MATROX_GET_DATA 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MATROX_CURSOR_CTL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct matrox_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *port_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct w1_bus_master *bus_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * These functions read and write DDC Data bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Using tristate pins, since i can't find any open-drain pin in whole motherboard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Unfortunately we can't connect to Intel's 82801xx IO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * since we don't know motherboard schema, which has pretty unused(may be not) GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * I've heard that PIIX also has open drain pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Port mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static __inline__ u8 matrox_w1_read_reg(struct matrox_device *dev, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writeb(reg, dev->port_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = readb(dev->port_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static __inline__ void matrox_w1_write_reg(struct matrox_device *dev, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writeb(reg, dev->port_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writeb(val, dev->port_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void matrox_w1_write_ddc_bit(void *data, u8 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct matrox_device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bit = dev->data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = matrox_w1_read_reg(dev, MATROX_GET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) matrox_w1_write_reg(dev, MATROX_GET_CONTROL, ((ret & ~dev->data_mask) | bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) matrox_w1_write_reg(dev, MATROX_GET_DATA, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static u8 matrox_w1_read_ddc_bit(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct matrox_device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = matrox_w1_read_reg(dev, MATROX_GET_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void matrox_w1_hw_init(struct matrox_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) matrox_w1_write_reg(dev, MATROX_GET_DATA, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) matrox_w1_write_reg(dev, MATROX_GET_CONTROL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int matrox_w1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct matrox_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (pdev->vendor != PCI_VENDOR_ID_MATROX || pdev->device != PCI_DEVICE_ID_MATROX_G400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev = kzalloc(sizeof(struct matrox_device) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) sizeof(struct w1_bus_master), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "%s: Failed to create new matrox_device object.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev->bus_master = (struct w1_bus_master *)(dev + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * True for G400, for some other we need resource 0, see drivers/video/matrox/matroxfb_base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev->phys_addr = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev->virt_addr = ioremap(dev->phys_addr, 16384);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!dev->virt_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(&pdev->dev, "%s: failed to ioremap(0x%lx, %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __func__, dev->phys_addr, 16384);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto err_out_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev->base_addr = dev->virt_addr + MATROX_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev->port_index = dev->base_addr + MATROX_PORT_INDEX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev->port_data = dev->base_addr + MATROX_PORT_DATA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev->data_mask = (MATROX_G400_DDC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) matrox_w1_hw_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev->bus_master->data = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev->bus_master->read_bit = &matrox_w1_read_ddc_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev->bus_master->write_bit = &matrox_w1_write_ddc_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) err = w1_add_master_device(dev->bus_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err_out_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev->found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_info(&pdev->dev, "Matrox G400 GPIO transport layer for 1-wire.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err_out_free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (dev->virt_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) iounmap(dev->virt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void matrox_w1_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct matrox_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (dev->found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) w1_remove_master_device(dev->bus_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iounmap(dev->virt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct pci_device_id matrox_w1_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { PCI_DEVICE(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_DEVICE_TABLE(pci, matrox_w1_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct pci_driver matrox_w1_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "matrox_w1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .id_table = matrox_w1_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .probe = matrox_w1_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .remove = matrox_w1_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) module_pci_driver(matrox_w1_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_AUTHOR("Evgeniy Polyakov <zbr@ioremap.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_DESCRIPTION("Driver for transport(Dallas 1-wire protocol) over VGA DDC(matrox gpio).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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