^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ds2482.c - provides i2c to w1-master bridge(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * The DS2482 is a sensor chip made by Dallas Semiconductor (Maxim).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * It is a I2C to 1-wire bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * There are two variations: -100 and -800, which have 1 or 8 1-wire ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The complete datasheet can be obtained from MAXIM's website at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/w1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Allow the active pullup to be disabled, default is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Note from the DS2482 datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The APU bit controls whether an active pullup (controlled slew-rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * transistor) or a passive pullup (Rwpu resistor) will be used to drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * a 1-Wire line from low to high. When APU = 0, active pullup is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * (resistor mode). Active Pullup should always be selected unless there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * only a single slave on the 1-Wire line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int ds2482_active_pullup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param_named(active_pullup, ds2482_active_pullup, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(active_pullup, "Active pullup (apply to all buses): " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "0-disable, 1-enable (default)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* extra configurations - e.g. 1WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int extra_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) module_param(extra_config, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_PARM_DESC(extra_config, "Extra Configuration settings 1=APU,2=PPM,3=SPU,8=1WS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The DS2482 registers - there are 3 registers that are addressed by a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * pointer. The read pointer is set by the last command executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * To read the data, issue a register read for any address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DS2482_CMD_RESET 0xF0 /* No param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DS2482_CMD_SET_READ_PTR 0xE1 /* Param: DS2482_PTR_CODE_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DS2482_CMD_CHANNEL_SELECT 0xC3 /* Param: Channel byte - DS2482-800 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DS2482_CMD_WRITE_CONFIG 0xD2 /* Param: Config byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DS2482_CMD_1WIRE_RESET 0xB4 /* Param: None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DS2482_CMD_1WIRE_SINGLE_BIT 0x87 /* Param: Bit byte (bit7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DS2482_CMD_1WIRE_WRITE_BYTE 0xA5 /* Param: Data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DS2482_CMD_1WIRE_READ_BYTE 0x96 /* Param: None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Note to read the byte, Set the ReadPtr to Data then read (any addr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DS2482_CMD_1WIRE_TRIPLET 0x78 /* Param: Dir byte (bit7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Values for DS2482_CMD_SET_READ_PTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS2482_PTR_CODE_STATUS 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DS2482_PTR_CODE_DATA 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DS2482_PTR_CODE_CHANNEL 0xD2 /* DS2482-800 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DS2482_PTR_CODE_CONFIG 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Configure Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The top 4 bits always read 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * To write, the top nibble must be the 1's compl. of the low nibble.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DS2482_REG_CFG_1WS 0x08 /* 1-wire speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DS2482_REG_CFG_SPU 0x04 /* strong pull-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DS2482_REG_CFG_PPM 0x02 /* presence pulse masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DS2482_REG_CFG_APU 0x01 /* active pull-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Write and verify codes for the CHANNEL_SELECT command (DS2482-800 only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * To set the channel, write the value at the index of the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Read and compare against the corresponding value to verify the change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const u8 ds2482_chan_wr[8] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0xF0, 0xE1, 0xD2, 0xC3, 0xB4, 0xA5, 0x96, 0x87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const u8 ds2482_chan_rd[8] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0xB8, 0xB1, 0xAA, 0xA3, 0x9C, 0x95, 0x8E, 0x87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Status Register bit definitions (read only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DS2482_REG_STS_DIR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DS2482_REG_STS_TSB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DS2482_REG_STS_SBR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DS2482_REG_STS_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DS2482_REG_STS_LL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DS2482_REG_STS_SD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DS2482_REG_STS_PPD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DS2482_REG_STS_1WB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Client data (each client gets its own)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ds2482_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ds2482_w1_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ds2482_data *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct w1_bus_master w1_bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ds2482_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mutex access_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 1-wire interface(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int w1_count; /* 1 or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ds2482_w1_chan w1_ch[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* per-device values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 read_prt; /* see DS2482_PTR_CODE_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 reg_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Helper to calculate values for configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @param conf the raw config value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @return the value w/ complements that can be written to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline u8 ds2482_calculate_config(u8 conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) conf |= extra_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ds2482_active_pullup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) conf |= DS2482_REG_CFG_APU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return conf | ((~conf & 0x0f) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Sets the read pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @param pdev The ds2482 client pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @param read_ptr see DS2482_PTR_CODE_xxx above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @return -1 on failure, 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline int ds2482_select_register(struct ds2482_data *pdev, u8 read_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (pdev->read_prt != read_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (i2c_smbus_write_byte_data(pdev->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DS2482_CMD_SET_READ_PTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) read_ptr) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pdev->read_prt = read_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Sends a command without a parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @param pdev The ds2482 client pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @param cmd DS2482_CMD_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * DS2482_CMD_1WIRE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * DS2482_CMD_1WIRE_READ_BYTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @return -1 on failure, 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline int ds2482_send_cmd(struct ds2482_data *pdev, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (i2c_smbus_write_byte(pdev->client, cmd) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pdev->read_prt = DS2482_PTR_CODE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Sends a command with a parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @param pdev The ds2482 client pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @param cmd DS2482_CMD_WRITE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * DS2482_CMD_1WIRE_SINGLE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * DS2482_CMD_1WIRE_WRITE_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * DS2482_CMD_1WIRE_TRIPLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @param byte The data to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @return -1 on failure, 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline int ds2482_send_cmd_data(struct ds2482_data *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 cmd, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (i2c_smbus_write_byte_data(pdev->client, cmd, byte) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* all cmds leave in STATUS, except CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pdev->read_prt = (cmd != DS2482_CMD_WRITE_CONFIG) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DS2482_PTR_CODE_STATUS : DS2482_PTR_CODE_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 1-Wire interface code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DS2482_WAIT_IDLE_TIMEOUT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Waits until the 1-wire interface is idle (not busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @param pdev Pointer to the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @return the last value read from status or -1 (failure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ds2482_wait_1wire_idle(struct ds2482_data *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int temp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!ds2482_select_register(pdev, DS2482_PTR_CODE_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) temp = i2c_smbus_read_byte(pdev->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } while ((temp >= 0) && (temp & DS2482_REG_STS_1WB) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (++retries < DS2482_WAIT_IDLE_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (retries >= DS2482_WAIT_IDLE_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pr_err("%s: timeout on channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __func__, pdev->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Selects a w1 channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * The 1-wire interface must be idle before calling this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @param pdev The ds2482 client pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @param channel 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @return -1 (failure) or 0 (success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int ds2482_set_channel(struct ds2482_data *pdev, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (i2c_smbus_write_byte_data(pdev->client, DS2482_CMD_CHANNEL_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ds2482_chan_wr[channel]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pdev->read_prt = DS2482_PTR_CODE_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pdev->channel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (i2c_smbus_read_byte(pdev->client) == ds2482_chan_rd[channel]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pdev->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Performs the touch-bit function, which writes a 0 or 1 and reads the level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @param data The ds2482 channel pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @param bit The level to write: 0 or non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @return The level read: 0 or 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static u8 ds2482_w1_touch_bit(void *data, u8 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct ds2482_w1_chan *pchan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ds2482_data *pdev = pchan->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int status = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mutex_lock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Select the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (pdev->w1_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ds2482_set_channel(pdev, pchan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Send the touch command, wait until 1WB == 0, return the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!ds2482_send_cmd_data(pdev, DS2482_CMD_1WIRE_SINGLE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bit ? 0xFF : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) status = ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mutex_unlock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return (status & DS2482_REG_STS_SBR) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Performs the triplet function, which reads two bits and writes a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * The bit written is determined by the two reads:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * 00 => dbit, 01 => 0, 10 => 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @param data The ds2482 channel pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @param dbit The direction to choose if both branches are valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @return b0=read1 b1=read2 b3=bit written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static u8 ds2482_w1_triplet(void *data, u8 dbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct ds2482_w1_chan *pchan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ds2482_data *pdev = pchan->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int status = (3 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mutex_lock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Select the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (pdev->w1_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ds2482_set_channel(pdev, pchan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Send the triplet command, wait until 1WB == 0, return the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!ds2482_send_cmd_data(pdev, DS2482_CMD_1WIRE_TRIPLET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dbit ? 0xFF : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) status = ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_unlock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Decode the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return (status >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Performs the write byte function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @param data The ds2482 channel pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * @param byte The value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void ds2482_w1_write_byte(void *data, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ds2482_w1_chan *pchan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ds2482_data *pdev = pchan->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mutex_lock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Select the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (pdev->w1_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ds2482_set_channel(pdev, pchan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Send the write byte command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ds2482_send_cmd_data(pdev, DS2482_CMD_1WIRE_WRITE_BYTE, byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mutex_unlock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Performs the read byte function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @param data The ds2482 channel pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @return The value read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static u8 ds2482_w1_read_byte(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct ds2482_w1_chan *pchan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct ds2482_data *pdev = pchan->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mutex_lock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Select the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (pdev->w1_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ds2482_set_channel(pdev, pchan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Send the read byte command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ds2482_send_cmd(pdev, DS2482_CMD_1WIRE_READ_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Wait until 1WB == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Select the data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ds2482_select_register(pdev, DS2482_PTR_CODE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Read the data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) result = i2c_smbus_read_byte(pdev->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mutex_unlock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Sends a reset on the 1-wire interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * @param data The ds2482 channel pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @return 0=Device present, 1=No device present or error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static u8 ds2482_w1_reset_bus(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct ds2482_w1_chan *pchan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct ds2482_data *pdev = pchan->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mutex_lock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Select the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pdev->w1_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ds2482_set_channel(pdev, pchan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Send the reset command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err = ds2482_send_cmd(pdev, DS2482_CMD_1WIRE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Wait until the reset is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err = ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) retval = !(err & DS2482_REG_STS_PPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* If the chip did reset since detect, re-config it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (err & DS2482_REG_STS_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ds2482_send_cmd_data(pdev, DS2482_CMD_WRITE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ds2482_calculate_config(0x00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mutex_unlock(&pdev->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static u8 ds2482_w1_set_pullup(void *data, int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct ds2482_w1_chan *pchan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ds2482_data *pdev = pchan->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* if delay is non-zero activate the pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * the strong pullup will be automatically deactivated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * by the master, so do not explicitly deactive it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* both waits are crucial, otherwise devices might not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * powered long enough, causing e.g. a w1_therm sensor to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * provide wrong conversion results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* note: it seems like both SPU and APU have to be set! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) retval = ds2482_send_cmd_data(pdev, DS2482_CMD_WRITE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ds2482_calculate_config(DS2482_REG_CFG_SPU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DS2482_REG_CFG_APU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ds2482_wait_1wire_idle(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int ds2482_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct ds2482_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) I2C_FUNC_SMBUS_WRITE_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) I2C_FUNC_SMBUS_BYTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!(data = kzalloc(sizeof(struct ds2482_data), GFP_KERNEL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Reset the device (sets the read_ptr to status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ds2482_send_cmd(data, DS2482_CMD_RESET) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_warn(&client->dev, "DS2482 reset failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Sleep at least 525ns to allow the reset to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ndelay(525);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Read the status byte - only reset bit and line should be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) temp1 = i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (temp1 != (DS2482_REG_STS_LL | DS2482_REG_STS_RST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_warn(&client->dev, "DS2482 reset status "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "0x%02X - not a DS2482\n", temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Detect the 8-port version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) data->w1_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ds2482_set_channel(data, 7) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) data->w1_count = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Set all config items to 0 (off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ds2482_send_cmd_data(data, DS2482_CMD_WRITE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ds2482_calculate_config(0x00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mutex_init(&data->access_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Register 1-wire interface(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (idx = 0; idx < data->w1_count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) data->w1_ch[idx].pdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) data->w1_ch[idx].channel = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Populate all the w1 bus master stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) data->w1_ch[idx].w1_bm.data = &data->w1_ch[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) data->w1_ch[idx].w1_bm.read_byte = ds2482_w1_read_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) data->w1_ch[idx].w1_bm.write_byte = ds2482_w1_write_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) data->w1_ch[idx].w1_bm.touch_bit = ds2482_w1_touch_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) data->w1_ch[idx].w1_bm.triplet = ds2482_w1_triplet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) data->w1_ch[idx].w1_bm.reset_bus = ds2482_w1_reset_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) data->w1_ch[idx].w1_bm.set_pullup = ds2482_w1_set_pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) err = w1_add_master_device(&data->w1_ch[idx].w1_bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) data->w1_ch[idx].pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto exit_w1_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) exit_w1_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for (idx = 0; idx < data->w1_count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (data->w1_ch[idx].pdev != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) w1_remove_master_device(&data->w1_ch[idx].w1_bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) exit_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int ds2482_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct ds2482_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Unregister the 1-wire bridge(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) for (idx = 0; idx < data->w1_count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (data->w1_ch[idx].pdev != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) w1_remove_master_device(&data->w1_ch[idx].w1_bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Free the memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Driver data (common to all clients)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct i2c_device_id ds2482_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { "ds2482", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_DEVICE_TABLE(i2c, ds2482_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct i2c_driver ds2482_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = "ds2482",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .probe = ds2482_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .remove = ds2482_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .id_table = ds2482_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_i2c_driver(ds2482_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_DESCRIPTION("DS2482 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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