^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * like hx4700).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Use consistent with the GNU GPL is permitted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * provided that this copyright notice is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * preserved in its entirety in all copies and derived works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/ds1wm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/w1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS1WM_CMD 0x00 /* R/W 4 bits command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DS1WM_DATA 0x01 /* R/W 8 bits, transmit/receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS1WM_INT 0x02 /* R/W interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DS1WM_CNTRL 0x05 /* R/W master control register (not used yet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS1WM_CMD_DQ_OUTPUT (1 << 2) /* write only - forces bus low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DS1WM_CMD_DQ_INPUT (1 << 3) /* read only - reflects state of bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DS1WM_CMD_RST (1 << 5) /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DS1WM_CMD_OD (1 << 7) /* overdrive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DS1WM_INT_PD (1 << 0) /* presence detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DS1WM_INT_PDR (1 << 1) /* presence detect result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DS1WM_INT_TBE (1 << 2) /* tx buffer empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DS1WM_INT_TSRE (1 << 3) /* tx shift register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DS1WM_INT_RBF (1 << 4) /* rx buffer full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DS1WM_INT_RSRF (1 << 5) /* rx shift register full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DS1WM_INTEN_EPD (1 << 0) /* enable presence detect int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DS1WM_INTEN_IAS (1 << 1) /* INTR active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DS1WM_INTEN_ETBE (1 << 2) /* enable tx buffer empty int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DS1WM_INTEN_ETMT (1 << 3) /* enable tx shift register empty int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DS1WM_INTEN_ERBF (1 << 4) /* enable rx buffer full int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS) /* all but INTR active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DS1WM_TIMEOUT (HZ * 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 1000000, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 2000000, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 3000000, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 4000000, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 5000000, 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 6000000, 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 7000000, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 8000000, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 10000000, 0x86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 12000000, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 14000000, 0x87 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 16000000, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 20000000, 0x8a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 24000000, 0x8d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 28000000, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 32000000, 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 40000000, 0x8e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 48000000, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 56000000, 0x8f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 64000000, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 80000000, 0x92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 96000000, 0x95 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 112000000, 0x93 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 128000000, 0x9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* you can continue this table, consult the OPERATION - CLOCK DIVISOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) section of the ds1wm spec sheet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ds1wm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int bus_shift; /* # of shifts to calc register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool is_hw_big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct mfd_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int slave_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void *reset_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void *read_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void *write_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int read_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* last byte received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 read_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* byte to write that makes all intr disabled, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* considering active_state (IAS) (optimization) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 int_en_reg_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int reset_recover_delay; /* see ds1wm.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ds1wm_data->is_hw_big_endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) switch (ds1wm_data->bus_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iowrite8(val, ds1wm_data->map + (reg << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) iowrite16be((u16)val, ds1wm_data->map + (reg << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) iowrite32be((u32)val, ds1wm_data->map + (reg << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (ds1wm_data->bus_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) iowrite8(val, ds1wm_data->map + (reg << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) iowrite16((u16)val, ds1wm_data->map + (reg << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) iowrite32((u32)val, ds1wm_data->map + (reg << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ds1wm_data->is_hw_big_endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) switch (ds1wm_data->bus_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = ioread8(ds1wm_data->map + (reg << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = ioread16be(ds1wm_data->map + (reg << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = ioread32be(ds1wm_data->map + (reg << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) switch (ds1wm_data->bus_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val = ioread8(ds1wm_data->map + (reg << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val = ioread16(ds1wm_data->map + (reg << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val = ioread32(ds1wm_data->map + (reg << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static irqreturn_t ds1wm_isr(int isr, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ds1wm_data *ds1wm_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* if no bits are set in int enable register (except the IAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) than go no further, reading the regs below has side effects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!(inten & DS1WM_INTEN_NOT_IAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ds1wm_write_register(ds1wm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* this read action clears the INTR and certain flags in ds1wm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) inten &= ~DS1WM_INTEN_ETMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) complete(ds1wm_data->write_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (intr & DS1WM_INT_RBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* this read clears the RBF flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DS1WM_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) inten &= ~DS1WM_INTEN_ERBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ds1wm_data->read_complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) complete(ds1wm_data->read_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) inten &= ~DS1WM_INTEN_EPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) complete(ds1wm_data->reset_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DECLARE_COMPLETION_ONSTACK(reset_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ds1wm_data->reset_complete = &reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* enable Presence detect only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ds1wm_data->int_en_reg_none);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ds1wm_data->reset_complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!timeleft) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!ds1wm_data->slave_present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ds1wm_data->reset_recover_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) msleep(ds1wm_data->reset_recover_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DECLARE_COMPLETION_ONSTACK(write_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ds1wm_data->write_complete = &write_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ds1wm_data->write_complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!timeleft) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DECLARE_COMPLETION_ONSTACK(read_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ds1wm_read_register(ds1wm_data, DS1WM_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ds1wm_data->read_complete = &read_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ds1wm_data->read_complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!timeleft) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ds1wm_data->read_error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ds1wm_data->read_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ds1wm_data->read_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int ds1wm_find_divisor(int gclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (gclk >= freq[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return freq[i].divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void ds1wm_up(struct ds1wm_data *ds1wm_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct device *dev = &ds1wm_data->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ds1wm_driver_data *plat = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ds1wm_data->cell->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ds1wm_data->cell->enable(ds1wm_data->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) divisor = ds1wm_find_divisor(plat->clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_dbg(dev, "found divisor 0x%x for clock %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) divisor, plat->clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (divisor == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(dev, "no suitable divisor for %dHz clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) plat->clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Let the w1 clock stabilize. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ds1wm_reset(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void ds1wm_down(struct ds1wm_data *ds1wm_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ds1wm_reset(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ds1wm_data->int_en_reg_none);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ds1wm_data->cell->disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ds1wm_data->cell->disable(ds1wm_data->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* w1 methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static u8 ds1wm_read_byte(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct ds1wm_data *ds1wm_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ds1wm_read(ds1wm_data, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void ds1wm_write_byte(void *data, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct ds1wm_data *ds1wm_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ds1wm_write(ds1wm_data, byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static u8 ds1wm_reset_bus(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct ds1wm_data *ds1wm_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ds1wm_reset(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void ds1wm_search(void *data, struct w1_master *master_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 search_type, w1_slave_found_callback slave_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ds1wm_data *ds1wm_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int ms_discrep_bit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u64 r = 0; /* holds the progress of the search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u64 r_prime, d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned slaves_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int pass = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ++pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (pass > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "too many attempts (100), search aborted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mutex_lock(&master_dev->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ds1wm_reset(ds1wm_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mutex_unlock(&master_dev->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "pass: %d reset error (or no slaves)\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ds1wm_write(ds1wm_data, search_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "pass: %d entering ASM\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "pass: %d beginning nibble loop\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) r_prime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* we work one nibble at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* each nibble is interleaved to form a byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned char resp, _r, _r_prime, _d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) _r = (r >> (4*i)) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) _r = ((_r & 0x1) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ((_r & 0x2) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ((_r & 0x4) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ((_r & 0x8) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* writes _r, then reads back: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) resp = ds1wm_read(ds1wm_data, _r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ds1wm_data->read_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "pass: %d nibble: %d read error\n", pass, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) _r_prime = ((resp & 0x02) >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ((resp & 0x08) >> 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ((resp & 0x20) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ((resp & 0x80) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) _d = ((resp & 0x01) >> 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ((resp & 0x04) >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ((resp & 0x10) >> 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ((resp & 0x40) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) r_prime |= (unsigned long long) _r_prime << (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) d |= (unsigned long long) _d << (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ds1wm_data->read_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_unlock(&master_dev->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "pass: %d read error, retrying\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "pass: %d r\': %0#18llx d:%0#18llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pass, r_prime, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "pass: %d nibble loop complete, exiting ASM\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "pass: %d resetting bus\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ds1wm_reset(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mutex_unlock(&master_dev->bus_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "pass: %d bus error, retrying\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) continue; /* start over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "pass: %d found %0#18llx\n", pass, r_prime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) slave_found(master_dev, r_prime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ++slaves_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "pass: %d complete, preparing next pass\n", pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* any discrepency found which we already choose the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) '1' branch is now is now irrelevant we reveal the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) next branch with this: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) d &= ~r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* find last bit set, i.e. the most signif. bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ms_discrep_bit = fls64(d) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "pass: %d new d:%0#18llx MS discrep bit:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pass, d, ms_discrep_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* prev_ms_discrep_bit = ms_discrep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) prepare for next ROM search: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ms_discrep_bit == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) r = (r & ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } /* end while true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "pass: %d total: %d search done ms d bit pos: %d\n", pass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) slaves_found, ms_discrep_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct w1_bus_master ds1wm_master = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .read_byte = ds1wm_read_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .write_byte = ds1wm_write_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .reset_bus = ds1wm_reset_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .search = ds1wm_search,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int ds1wm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct ds1wm_data *ds1wm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct ds1wm_driver_data *plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 inten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ds1wm_data = devm_kzalloc(&pdev->dev, sizeof(*ds1wm_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!ds1wm_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) platform_set_drvdata(pdev, ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ds1wm_data->map = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!ds1wm_data->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ds1wm_data->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ds1wm_data->cell = mfd_get_cell(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!ds1wm_data->cell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) plat = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!plat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* how many bits to shift register number to get register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (plat->bus_shift > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "illegal bus shift %d, not written",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ds1wm_data->bus_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ds1wm_data->bus_shift = plat->bus_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* make sure resource has space for 8 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "memory resource size %d to small, should be %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (int)resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 8 << ds1wm_data->bus_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ds1wm_data->irq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ds1wm_data->reset_recover_delay = plat->reset_recover_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Mask interrupts, set IAS before claiming interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ds1wm_write_register(ds1wm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (res->flags & IORESOURCE_IRQ_LOWEDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (res->flags & IORESOURCE_IRQ_HIGHLEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (res->flags & IORESOURCE_IRQ_LOWLEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) IRQF_SHARED, "ds1wm", ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "devm_request_irq %d failed with errno %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ds1wm_data->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ds1wm_up(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ds1wm_master.data = (void *)ds1wm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = w1_add_master_device(&ds1wm_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_dbg(&ds1wm_data->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "ds1wm: probe successful, IAS: %d, rec.delay: %d, clockrate: %d, bus-shift: %d, is Hw Big Endian: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) plat->active_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) plat->reset_recover_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) plat->clock_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ds1wm_data->bus_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ds1wm_data->is_hw_big_endian);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ds1wm_down(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ds1wm_down(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int ds1wm_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ds1wm_up(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define ds1wm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ds1wm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int ds1wm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) w1_remove_master_device(&ds1wm_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ds1wm_down(ds1wm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static struct platform_driver ds1wm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .name = "ds1wm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .probe = ds1wm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .remove = ds1wm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .suspend = ds1wm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .resume = ds1wm_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int __init ds1wm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pr_info("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return platform_driver_register(&ds1wm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void __exit ds1wm_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) platform_driver_unregister(&ds1wm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) module_init(ds1wm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) module_exit(ds1wm_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "Matt Reimer <mreimer@vpop.net>,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "Jean-Francois Dagenais <dagenaisj@sonatest.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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