^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tsi148.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the Tundra TSI148 VME Bridge chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Tom Armistead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Updated and maintained by Ajit Prem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2004 Motorola Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef TSI148_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TSI148_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef PCI_VENDOR_ID_TUNDRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_VENDOR_ID_TUNDRA 0x10e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef PCI_DEVICE_ID_TUNDRA_TSI148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_DEVICE_ID_TUNDRA_TSI148 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Define the number of each that the Tsi148 supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TSI148_MAX_MASTER 8 /* Max Master Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TSI148_MAX_DMA 2 /* Max DMA Controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Structure used to hold driver specific information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct tsi148_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *base; /* Base Address of device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) wait_queue_head_t dma_queue[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) wait_queue_head_t iack_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void (*lm_callback[4])(void *); /* Called in interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void *lm_data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void *crcsr_kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dma_addr_t crcsr_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct vme_master_resource *flush_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mutex vme_rmw; /* Only one RMW cycle at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mutex vme_int; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Only one VME interrupt can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * generated at a time, provide locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Layout of a DMAC Linked-List Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Note: This structure is accessed via the chip and therefore must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * correctly laid out - It must also be aligned on 64-bit boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct tsi148_dma_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __be32 dsau; /* Source Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __be32 dsal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __be32 ddau; /* Destination Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __be32 ddal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __be32 dsat; /* Source attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __be32 ddat; /* Destination attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __be32 dnlau; /* Next link address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __be32 dnlal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __be32 dcnt; /* Byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __be32 ddbs; /* 2eSST Broadcast select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct tsi148_dma_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * The descriptor needs to be aligned on a 64-bit boundary, we increase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * the chance of this by putting it first in the structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct tsi148_dma_descriptor descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * TSI148 ASIC register structure overlays and bit field definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Note: Tsi148 Register Group (CRG) consists of the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * combination of registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * PCFS - PCI Configuration Space Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * LCSR - Local Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * GCSR - Global Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * CR/CSR - Subset of Configuration ROM /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Command/Status Registers (CRG + $004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TSI148_PCFS_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TSI148_PCFS_CSR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TSI148_PCFS_CLASS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TSI148_PCFS_MISC0 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TSI148_PCFS_MBARL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TSI148_PCFS_MBARU 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TSI148_PCFS_SUBID 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TSI148_PCFS_CAPP 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TSI148_PCFS_MISC1 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TSI148_PCFS_XCAPP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TSI148_PCFS_XSTAT 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * LCSR definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Outbound Translations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TSI148_LCSR_OT0_OTSAU 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TSI148_LCSR_OT0_OTSAL 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TSI148_LCSR_OT0_OTEAU 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TSI148_LCSR_OT0_OTEAL 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TSI148_LCSR_OT0_OTOFU 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TSI148_LCSR_OT0_OTOFL 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TSI148_LCSR_OT0_OTBS 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TSI148_LCSR_OT0_OTAT 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TSI148_LCSR_OT1_OTSAU 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TSI148_LCSR_OT1_OTSAL 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TSI148_LCSR_OT1_OTEAU 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TSI148_LCSR_OT1_OTEAL 0x12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TSI148_LCSR_OT1_OTOFU 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TSI148_LCSR_OT1_OTOFL 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TSI148_LCSR_OT1_OTBS 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TSI148_LCSR_OT1_OTAT 0x13C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TSI148_LCSR_OT2_OTSAU 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TSI148_LCSR_OT2_OTSAL 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TSI148_LCSR_OT2_OTEAU 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TSI148_LCSR_OT2_OTEAL 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TSI148_LCSR_OT2_OTOFU 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TSI148_LCSR_OT2_OTOFL 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TSI148_LCSR_OT2_OTBS 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TSI148_LCSR_OT2_OTAT 0x15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TSI148_LCSR_OT3_OTSAU 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TSI148_LCSR_OT3_OTSAL 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TSI148_LCSR_OT3_OTEAU 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TSI148_LCSR_OT3_OTEAL 0x16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TSI148_LCSR_OT3_OTOFU 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TSI148_LCSR_OT3_OTOFL 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TSI148_LCSR_OT3_OTBS 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TSI148_LCSR_OT3_OTAT 0x17C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TSI148_LCSR_OT4_OTSAU 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TSI148_LCSR_OT4_OTSAL 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TSI148_LCSR_OT4_OTEAU 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TSI148_LCSR_OT4_OTEAL 0x18C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TSI148_LCSR_OT4_OTOFU 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TSI148_LCSR_OT4_OTOFL 0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TSI148_LCSR_OT4_OTBS 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TSI148_LCSR_OT4_OTAT 0x19C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TSI148_LCSR_OT5_OTSAU 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TSI148_LCSR_OT5_OTSAL 0x1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TSI148_LCSR_OT5_OTEAU 0x1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TSI148_LCSR_OT5_OTEAL 0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TSI148_LCSR_OT5_OTOFU 0x1B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TSI148_LCSR_OT5_OTOFL 0x1B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TSI148_LCSR_OT5_OTBS 0x1B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TSI148_LCSR_OT5_OTAT 0x1BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TSI148_LCSR_OT6_OTSAU 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TSI148_LCSR_OT6_OTSAL 0x1C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TSI148_LCSR_OT6_OTEAU 0x1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TSI148_LCSR_OT6_OTEAL 0x1CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TSI148_LCSR_OT6_OTOFU 0x1D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TSI148_LCSR_OT6_OTOFL 0x1D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TSI148_LCSR_OT6_OTBS 0x1D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TSI148_LCSR_OT6_OTAT 0x1DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TSI148_LCSR_OT7_OTSAU 0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TSI148_LCSR_OT7_OTSAL 0x1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TSI148_LCSR_OT7_OTEAU 0x1E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TSI148_LCSR_OT7_OTEAL 0x1EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TSI148_LCSR_OT7_OTOFU 0x1F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TSI148_LCSR_OT7_OTOFL 0x1F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TSI148_LCSR_OT7_OTBS 0x1F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TSI148_LCSR_OT7_OTAT 0x1FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TSI148_LCSR_OT0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TSI148_LCSR_OT1 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TSI148_LCSR_OT2 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TSI148_LCSR_OT3 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TSI148_LCSR_OT4 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TSI148_LCSR_OT5 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TSI148_LCSR_OT6 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TSI148_LCSR_OT7 0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TSI148_LCSR_OT2, TSI148_LCSR_OT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TSI148_LCSR_OT4, TSI148_LCSR_OT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) TSI148_LCSR_OT6, TSI148_LCSR_OT7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TSI148_LCSR_OFFSET_OTSAU 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TSI148_LCSR_OFFSET_OTSAL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TSI148_LCSR_OFFSET_OTEAU 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TSI148_LCSR_OFFSET_OTEAL 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TSI148_LCSR_OFFSET_OTOFU 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TSI148_LCSR_OFFSET_OTOFL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TSI148_LCSR_OFFSET_OTBS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TSI148_LCSR_OFFSET_OTAT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * VMEbus interrupt ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * offset 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TSI148_LCSR_VIACK1 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TSI148_LCSR_VIACK2 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TSI148_LCSR_VIACK3 0x20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TSI148_LCSR_VIACK4 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TSI148_LCSR_VIACK5 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TSI148_LCSR_VIACK6 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TSI148_LCSR_VIACK7 0x21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * RMW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * offset 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TSI148_LCSR_RMWAU 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TSI148_LCSR_RMWAL 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TSI148_LCSR_RMWEN 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TSI148_LCSR_RMWC 0x22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TSI148_LCSR_RMWS 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * VMEbus control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * offset 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TSI148_LCSR_VMCTRL 0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TSI148_LCSR_VCTRL 0x238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TSI148_LCSR_VSTAT 0x23C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * PCI status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * offset 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TSI148_LCSR_PSTAT 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * VME filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * offset 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TSI148_LCSR_VMEFL 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * VME exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * offset 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TSI148_LCSR_VEAU 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TSI148_LCSR_VEAL 0x264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TSI148_LCSR_VEAT 0x268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * PCI error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * offset 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TSI148_LCSR_EDPAU 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TSI148_LCSR_EDPAL 0x274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TSI148_LCSR_EDPXA 0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TSI148_LCSR_EDPXS 0x27C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TSI148_LCSR_EDPAT 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Inbound Translations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * offset 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TSI148_LCSR_IT0_ITSAU 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TSI148_LCSR_IT0_ITSAL 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TSI148_LCSR_IT0_ITEAU 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TSI148_LCSR_IT0_ITEAL 0x30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TSI148_LCSR_IT0_ITOFU 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TSI148_LCSR_IT0_ITOFL 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TSI148_LCSR_IT0_ITAT 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TSI148_LCSR_IT1_ITSAU 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TSI148_LCSR_IT1_ITSAL 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TSI148_LCSR_IT1_ITEAU 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TSI148_LCSR_IT1_ITEAL 0x32C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TSI148_LCSR_IT1_ITOFU 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TSI148_LCSR_IT1_ITOFL 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TSI148_LCSR_IT1_ITAT 0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TSI148_LCSR_IT2_ITSAU 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TSI148_LCSR_IT2_ITSAL 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TSI148_LCSR_IT2_ITEAU 0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TSI148_LCSR_IT2_ITEAL 0x34C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TSI148_LCSR_IT2_ITOFU 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TSI148_LCSR_IT2_ITOFL 0x354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TSI148_LCSR_IT2_ITAT 0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TSI148_LCSR_IT3_ITSAU 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TSI148_LCSR_IT3_ITSAL 0x364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TSI148_LCSR_IT3_ITEAU 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TSI148_LCSR_IT3_ITEAL 0x36C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TSI148_LCSR_IT3_ITOFU 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TSI148_LCSR_IT3_ITOFL 0x374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TSI148_LCSR_IT3_ITAT 0x378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TSI148_LCSR_IT4_ITSAU 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TSI148_LCSR_IT4_ITSAL 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TSI148_LCSR_IT4_ITEAU 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TSI148_LCSR_IT4_ITEAL 0x38C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TSI148_LCSR_IT4_ITOFU 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TSI148_LCSR_IT4_ITOFL 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TSI148_LCSR_IT4_ITAT 0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TSI148_LCSR_IT5_ITSAU 0x3A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TSI148_LCSR_IT5_ITSAL 0x3A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TSI148_LCSR_IT5_ITEAU 0x3A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TSI148_LCSR_IT5_ITEAL 0x3AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TSI148_LCSR_IT5_ITOFU 0x3B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TSI148_LCSR_IT5_ITOFL 0x3B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TSI148_LCSR_IT5_ITAT 0x3B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TSI148_LCSR_IT6_ITSAU 0x3C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TSI148_LCSR_IT6_ITSAL 0x3C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TSI148_LCSR_IT6_ITEAU 0x3C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TSI148_LCSR_IT6_ITEAL 0x3CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TSI148_LCSR_IT6_ITOFU 0x3D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TSI148_LCSR_IT6_ITOFL 0x3D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TSI148_LCSR_IT6_ITAT 0x3D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TSI148_LCSR_IT7_ITSAU 0x3E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TSI148_LCSR_IT7_ITSAL 0x3E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TSI148_LCSR_IT7_ITEAU 0x3E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TSI148_LCSR_IT7_ITEAL 0x3EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TSI148_LCSR_IT7_ITOFU 0x3F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TSI148_LCSR_IT7_ITOFL 0x3F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TSI148_LCSR_IT7_ITAT 0x3F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TSI148_LCSR_IT0 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TSI148_LCSR_IT1 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TSI148_LCSR_IT2 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TSI148_LCSR_IT3 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TSI148_LCSR_IT4 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TSI148_LCSR_IT5 0x3A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TSI148_LCSR_IT6 0x3C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TSI148_LCSR_IT7 0x3E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) TSI148_LCSR_IT2, TSI148_LCSR_IT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) TSI148_LCSR_IT4, TSI148_LCSR_IT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) TSI148_LCSR_IT6, TSI148_LCSR_IT7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TSI148_LCSR_OFFSET_ITSAU 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TSI148_LCSR_OFFSET_ITSAL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TSI148_LCSR_OFFSET_ITEAU 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TSI148_LCSR_OFFSET_ITEAL 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TSI148_LCSR_OFFSET_ITOFU 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TSI148_LCSR_OFFSET_ITOFL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TSI148_LCSR_OFFSET_ITAT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Inbound Translation GCSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * offset 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TSI148_LCSR_GBAU 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TSI148_LCSR_GBAL 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TSI148_LCSR_GCSRAT 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Inbound Translation CRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * offset 40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TSI148_LCSR_CBAU 0x40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define TSI148_LCSR_CBAL 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TSI148_LCSR_CSRAT 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Inbound Translation CR/CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * CRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * offset 418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TSI148_LCSR_CROU 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define TSI148_LCSR_CROL 0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define TSI148_LCSR_CRAT 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Inbound Translation Location Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * offset 424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TSI148_LCSR_LMBAU 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TSI148_LCSR_LMBAL 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TSI148_LCSR_LMAT 0x42C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * VMEbus Interrupt Control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * offset 430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TSI148_LCSR_BCU 0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TSI148_LCSR_BCL 0x434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TSI148_LCSR_BPGTR 0x438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TSI148_LCSR_BPCTR 0x43C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TSI148_LCSR_VICR 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Local Bus Interrupt Control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * offset 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define TSI148_LCSR_INTEN 0x448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define TSI148_LCSR_INTEO 0x44C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define TSI148_LCSR_INTS 0x450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define TSI148_LCSR_INTC 0x454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define TSI148_LCSR_INTM1 0x458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define TSI148_LCSR_INTM2 0x45C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * DMA Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * offset 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TSI148_LCSR_DCTL0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TSI148_LCSR_DSTA0 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TSI148_LCSR_DCSAU0 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define TSI148_LCSR_DCSAL0 0x50C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TSI148_LCSR_DCDAU0 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define TSI148_LCSR_DCDAL0 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TSI148_LCSR_DCLAU0 0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define TSI148_LCSR_DCLAL0 0x51C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define TSI148_LCSR_DSAU0 0x520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define TSI148_LCSR_DSAL0 0x524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define TSI148_LCSR_DDAU0 0x528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define TSI148_LCSR_DDAL0 0x52C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TSI148_LCSR_DSAT0 0x530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define TSI148_LCSR_DDAT0 0x534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define TSI148_LCSR_DNLAU0 0x538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define TSI148_LCSR_DNLAL0 0x53C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TSI148_LCSR_DCNT0 0x540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define TSI148_LCSR_DDBS0 0x544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TSI148_LCSR_DCTL1 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TSI148_LCSR_DSTA1 0x584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define TSI148_LCSR_DCSAU1 0x588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TSI148_LCSR_DCSAL1 0x58C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TSI148_LCSR_DCDAU1 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TSI148_LCSR_DCDAL1 0x594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TSI148_LCSR_DCLAU1 0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TSI148_LCSR_DCLAL1 0x59C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TSI148_LCSR_DSAU1 0x5A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TSI148_LCSR_DSAL1 0x5A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define TSI148_LCSR_DDAU1 0x5A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define TSI148_LCSR_DDAL1 0x5AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TSI148_LCSR_DSAT1 0x5B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TSI148_LCSR_DDAT1 0x5B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define TSI148_LCSR_DNLAU1 0x5B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TSI148_LCSR_DNLAL1 0x5BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TSI148_LCSR_DCNT1 0x5C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define TSI148_LCSR_DDBS1 0x5C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define TSI148_LCSR_DMA0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define TSI148_LCSR_DMA1 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) TSI148_LCSR_DMA1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define TSI148_LCSR_OFFSET_DCTL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define TSI148_LCSR_OFFSET_DSTA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define TSI148_LCSR_OFFSET_DCSAU 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define TSI148_LCSR_OFFSET_DCSAL 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define TSI148_LCSR_OFFSET_DCDAU 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define TSI148_LCSR_OFFSET_DCDAL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define TSI148_LCSR_OFFSET_DCLAU 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define TSI148_LCSR_OFFSET_DCLAL 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define TSI148_LCSR_OFFSET_DSAU 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define TSI148_LCSR_OFFSET_DSAL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define TSI148_LCSR_OFFSET_DDAU 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define TSI148_LCSR_OFFSET_DDAL 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define TSI148_LCSR_OFFSET_DSAT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TSI148_LCSR_OFFSET_DDAT 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define TSI148_LCSR_OFFSET_DNLAU 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define TSI148_LCSR_OFFSET_DNLAL 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define TSI148_LCSR_OFFSET_DCNT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define TSI148_LCSR_OFFSET_DDBS 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * GCSR Register Group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * GCSR CRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * offset 00 600 - DEVI/VENI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * offset 04 604 - CTRL/GA/REVID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * offset 08 608 - Semaphore3/2/1/0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * offset 0C 60C - Seamphore7/6/5/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define TSI148_GCSR_ID 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define TSI148_GCSR_CSR 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define TSI148_GCSR_SEMA0 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define TSI148_GCSR_SEMA1 0x60C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Mail Box
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * GCSR CRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * offset 10 610 - Mailbox0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define TSI148_GCSR_MBOX0 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define TSI148_GCSR_MBOX1 0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define TSI148_GCSR_MBOX2 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define TSI148_GCSR_MBOX3 0x61C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TSI148_GCSR_MBOX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) TSI148_GCSR_MBOX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) TSI148_GCSR_MBOX3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * CR/CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * CR/CSR CRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * offset 7FFF4 FF4 - CSRBCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * offset 7FFF8 FF8 - CSRBSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * offset 7FFFC FFC - CBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define TSI148_CSRBCR 0xFF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define TSI148_CSRBSR 0xFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define TSI148_CBAR 0xFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * TSI148 Register Bit Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * PFCS Register Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define TSI148_PCFS_STAT_RCPVE (1<<15) /* Detected Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define TSI148_PCFS_STAT_DPAR (1<<8) /* Data Parity Err Reported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Revision ID/Class Code Registers (CRG +$008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define TSI148_PCFS_CLAS_M (0xFF<<24) /* Class ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define TSI148_PCFS_SUBCLAS_M (0xFF<<16) /* Sub-Class ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define TSI148_PCFS_PROGIF_M (0xFF<<8) /* Sub-Class ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define TSI148_PCFS_REVID_M (0xFF<<0) /* Rev ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define TSI148_PCFS_HEAD_M (0xFF<<16) /* Master Lat Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define TSI148_PCFS_MLAT_M (0xFF<<8) /* Master Lat Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define TSI148_PCFS_CLSZ_M (0xFF<<0) /* Cache Line Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Memory Base Address Lower Reg (CRG + $010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Message Signaled Interrupt Capabilities Register (CRG + $040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define TSI148_PCFS_MSICAP_64BAC (1<<7) /* 64-bit Address Capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define TSI148_PCFS_MSICAP_MME_M (7<<4) /* Multiple Msg Enable Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define TSI148_PCFS_MSICAP_MMC_M (7<<1) /* Multiple Msg Capable Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define TSI148_PCFS_MSICAP_MSIEN (1<<0) /* Msg signaled INT Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Message Address Lower Register (CRG +$044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define TSI148_PCFS_MSIAL_M (0x3FFFFFFF<<2) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Message Data Register (CRG + 4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define TSI148_PCFS_MSIMD_M (0xFFFF<<0) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * PCI-X Capabilities Register (CRG + $050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * PCI-X Status Register (CRG +$054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Received Split Comp Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * LCSR Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * Outbound Translation Starting Address Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TSI148_LCSR_OTSAL_M (0xFFFF<<16) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Outbound Translation Ending Address Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define TSI148_LCSR_OTEAL_M (0xFFFF<<16) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * Outbound Translation Offset Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define TSI148_LCSR_OTOFFL_M (0xFFFF<<16) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Outbound Translation 2eSST Broadcast Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define TSI148_LCSR_OTBS_M (0xFFFFF<<0) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Outbound Translation Attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8) /* 2eSST Bcast Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0) /* User1 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0) /* User2 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define TSI148_LCSR_OTAT_AMODE_USER3 (10<<0) /* User3 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define TSI148_LCSR_OTAT_AMODE_USER4 (11<<0) /* User4 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * VME Master Control Register CRG+$234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define TSI148_LCSR_VMCTRL_ATO_2M (3<<16) /* 2 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define TSI148_LCSR_VMCTRL_ATO_8M (4<<16) /* 8 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define TSI148_LCSR_VMCTRL_ATO_32M (5<<16) /* 32 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define TSI148_LCSR_VMCTRL_ATO_128M (6<<16) /* 128 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define TSI148_LCSR_VMCTRL_ATO_DIS (7<<16) /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * VMEbus Control Register CRG+$238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define TSI148_LCSR_VCTRL_LRE (1<<31) /* Late Retry Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define TSI148_LCSR_VCTRL_DLT_256 (5<<24) /* 256 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define TSI148_LCSR_VCTRL_DLT_512 (6<<24) /* 512 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define TSI148_LCSR_VCTRL_DLT_1024 (7<<24) /* 1024 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define TSI148_LCSR_VCTRL_DLT_2048 (8<<24) /* 2048 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define TSI148_LCSR_VCTRL_DLT_4096 (9<<24) /* 4096 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define TSI148_LCSR_VCTRL_DLT_8192 (0xA<<24) /* 8192 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define TSI148_LCSR_VCTRL_GTO_DIS (7<<0) /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * VMEbus Status Register CRG + $23C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define TSI148_LCSR_VSTAT_BRDFL (1<<14) /* Board fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * PCI Configuration Status Register CRG+$240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define TSI148_LCSR_PSTAT_REQ64S (1<<6) /* Request 64 status set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define TSI148_LCSR_PSTAT_M66ENS (1<<5) /* M66ENS 66Mhz enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define TSI148_LCSR_PSTAT_FRAMES (1<<4) /* Frame Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define TSI148_LCSR_PSTAT_IRDYS (1<<3) /* IRDY status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define TSI148_LCSR_PSTAT_DEVSELS (1<<2) /* DEVL status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define TSI148_LCSR_PSTAT_STOPS (1<<1) /* STOP status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define TSI148_LCSR_PSTAT_TRDYS (1<<0) /* TRDY status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * VMEbus Exception Attributes Register CRG + $268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define TSI148_LCSR_VEAT_VES (1<<31) /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define TSI148_LCSR_VEAT_VEOF (1<<30) /* Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define TSI148_LCSR_VEAT_VESCL (1<<29) /* Status Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define TSI148_LCSR_VEAT_2EOT (1<<21) /* 2e Odd Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define TSI148_LCSR_VEAT_2EST (1<<20) /* 2e Slave terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define TSI148_LCSR_VEAT_BERR (1<<19) /* Bus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define TSI148_LCSR_VEAT_LWORD (1<<18) /* LWORD_ signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define TSI148_LCSR_VEAT_WRITE (1<<17) /* WRITE_ signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define TSI148_LCSR_VEAT_IACK (1<<16) /* IACK_ signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define TSI148_LCSR_VEAT_DS1 (1<<15) /* DS1_ signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define TSI148_LCSR_VEAT_DS0 (1<<14) /* DS0_ signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define TSI148_LCSR_EDPAT_EDPCL (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * Inbound Translation Starting Address Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define TSI148_LCSR_ITSAL24_M (0x00FFF<<12) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Inbound Translation Ending Address Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define TSI148_LCSR_ITEAL24_M (0x00FFF<<12) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Inbound Translation Offset Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * Inbound Translation Attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * GCSR Base Address Lower Address CRG +$404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * GCSR Attribute Register CRG + $408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define TSI148_LCSR_GCSRAT_AS_A16 (0<<4) /* Address Space 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define TSI148_LCSR_GCSRAT_AS_A24 (1<<4) /* Address Space 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define TSI148_LCSR_GCSRAT_AS_A32 (2<<4) /* Address Space 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define TSI148_LCSR_GCSRAT_AS_A64 (4<<4) /* Address Space 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * CRG Base Address Lower Address CRG + $410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define TSI148_LCSR_CBAL_M (0xFFFFF<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * CRG Attribute Register CRG + $414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define TSI148_LCSR_CRGAT_AS_A16 (0<<4) /* Address Space 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define TSI148_LCSR_CRGAT_AS_A24 (1<<4) /* Address Space 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define TSI148_LCSR_CRGAT_AS_A32 (2<<4) /* Address Space 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define TSI148_LCSR_CRGAT_AS_A64 (4<<4) /* Address Space 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * CR/CSR Offset Lower Register CRG + $41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define TSI148_LCSR_CROL_M (0x1FFF<<19) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * CR/CSR Attribute register CRG + $420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * Location Monitor base address lower register CRG + $428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Location Monitor Attribute Register CRG + $42C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define TSI148_LCSR_LMAT_AS_A16 (0<<4) /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define TSI148_LCSR_LMAT_AS_A24 (1<<4) /* A24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define TSI148_LCSR_LMAT_AS_A64 (4<<4) /* A64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Broadcast Pulse Generator Timer Register CRG + $438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * Broadcast Programmable Clock Timer Register CRG + $43C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * VMEbus Interrupt Control Register CRG + $43C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define TSI148_LCSR_VICR_CNTS_M (3<<22) /* Cntr Source MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define TSI148_LCSR_VICR_CNTS_DIS (1<<22) /* Cntr Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interrupt MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interrupt Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define TSI148_LCSR_VICR_IRQIF_M (3<<18) /* IRQ1* Function MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define TSI148_LCSR_VICR_IRQIF_NORM (1<<18) /* Normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18) /* Pulse Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define TSI148_LCSR_VICR_IRQIF_PROG (3<<18) /* Programmable Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define TSI148_LCSR_VICR_IRQ2F_M (3<<16) /* IRQ2* Function MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16) /* Normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16) /* Pulse Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16) /* Programmable Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define TSI148_LCSR_VICR_BIP (1<<15) /* Broadcast Interrupt Pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define TSI148_LCSR_VICR_IRQC (1<<12) /* VMEbus IRQ Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define TSI148_LCSR_VICR_STID_M (0xFF<<0) /* Status/ID Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * Interrupt Enable Register CRG + $440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define TSI148_LCSR_INTEN_DMA1EN (1<<25) /* DMAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define TSI148_LCSR_INTEN_DMA0EN (1<<24) /* DMAC 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define TSI148_LCSR_INTEN_LM3EN (1<<23) /* Location Monitor 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define TSI148_LCSR_INTEN_LM2EN (1<<22) /* Location Monitor 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define TSI148_LCSR_INTEN_LM1EN (1<<21) /* Location Monitor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define TSI148_LCSR_INTEN_LM0EN (1<<20) /* Location Monitor 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define TSI148_LCSR_INTEN_MB3EN (1<<19) /* Mail Box 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define TSI148_LCSR_INTEN_MB2EN (1<<18) /* Mail Box 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define TSI148_LCSR_INTEN_MB1EN (1<<17) /* Mail Box 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define TSI148_LCSR_INTEN_MB0EN (1<<16) /* Mail Box 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define TSI148_LCSR_INTEN_PERREN (1<<13) /* PCI/X Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define TSI148_LCSR_INTEN_VERREN (1<<12) /* VMEbus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define TSI148_LCSR_INTEN_VIEEN (1<<11) /* VMEbus IRQ Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define TSI148_LCSR_INTEN_IACKEN (1<<10) /* IACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define TSI148_LCSR_INTEN_SYSFLEN (1<<9) /* System Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define TSI148_LCSR_INTEN_ACFLEN (1<<8) /* AC Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define TSI148_LCSR_INTEN_IRQ7EN (1<<7) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define TSI148_LCSR_INTEN_IRQ6EN (1<<6) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define TSI148_LCSR_INTEN_IRQ5EN (1<<5) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define TSI148_LCSR_INTEN_IRQ4EN (1<<4) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define TSI148_LCSR_INTEN_IRQ3EN (1<<3) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define TSI148_LCSR_INTEN_IRQ2EN (1<<2) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define TSI148_LCSR_INTEN_IRQ1EN (1<<1) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) TSI148_LCSR_INTEN_LM1EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) TSI148_LCSR_INTEN_LM2EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) TSI148_LCSR_INTEN_LM3EN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) TSI148_LCSR_INTEN_IRQ2EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) TSI148_LCSR_INTEN_IRQ3EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) TSI148_LCSR_INTEN_IRQ4EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) TSI148_LCSR_INTEN_IRQ5EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) TSI148_LCSR_INTEN_IRQ6EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) TSI148_LCSR_INTEN_IRQ7EN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * Interrupt Enable Out Register CRG + $444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define TSI148_LCSR_INTEO_DMA1EO (1<<25) /* DMAC 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define TSI148_LCSR_INTEO_DMA0EO (1<<24) /* DMAC 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define TSI148_LCSR_INTEO_LM3EO (1<<23) /* Loc Monitor 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define TSI148_LCSR_INTEO_LM2EO (1<<22) /* Loc Monitor 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define TSI148_LCSR_INTEO_LM1EO (1<<21) /* Loc Monitor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define TSI148_LCSR_INTEO_LM0EO (1<<20) /* Location Monitor 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define TSI148_LCSR_INTEO_MB3EO (1<<19) /* Mail Box 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define TSI148_LCSR_INTEO_MB2EO (1<<18) /* Mail Box 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define TSI148_LCSR_INTEO_MB1EO (1<<17) /* Mail Box 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define TSI148_LCSR_INTEO_MB0EO (1<<16) /* Mail Box 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define TSI148_LCSR_INTEO_PERREO (1<<13) /* PCI/X Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define TSI148_LCSR_INTEO_VERREO (1<<12) /* VMEbus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define TSI148_LCSR_INTEO_VIEEO (1<<11) /* VMEbus IRQ Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define TSI148_LCSR_INTEO_IACKEO (1<<10) /* IACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define TSI148_LCSR_INTEO_SYSFLEO (1<<9) /* System Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define TSI148_LCSR_INTEO_ACFLEO (1<<8) /* AC Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define TSI148_LCSR_INTEO_IRQ7EO (1<<7) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define TSI148_LCSR_INTEO_IRQ6EO (1<<6) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define TSI148_LCSR_INTEO_IRQ5EO (1<<5) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define TSI148_LCSR_INTEO_IRQ4EO (1<<4) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define TSI148_LCSR_INTEO_IRQ3EO (1<<3) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define TSI148_LCSR_INTEO_IRQ2EO (1<<2) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define TSI148_LCSR_INTEO_IRQ1EO (1<<1) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) TSI148_LCSR_INTEO_LM1EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) TSI148_LCSR_INTEO_LM2EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) TSI148_LCSR_INTEO_LM3EO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) TSI148_LCSR_INTEO_IRQ2EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) TSI148_LCSR_INTEO_IRQ3EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) TSI148_LCSR_INTEO_IRQ4EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) TSI148_LCSR_INTEO_IRQ5EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) TSI148_LCSR_INTEO_IRQ6EO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) TSI148_LCSR_INTEO_IRQ7EO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * Interrupt Status Register CRG + $448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define TSI148_LCSR_INTS_DMA1S (1<<25) /* DMA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define TSI148_LCSR_INTS_DMA0S (1<<24) /* DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define TSI148_LCSR_INTS_LM3S (1<<23) /* Location Monitor 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define TSI148_LCSR_INTS_LM2S (1<<22) /* Location Monitor 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define TSI148_LCSR_INTS_LM1S (1<<21) /* Location Monitor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define TSI148_LCSR_INTS_LM0S (1<<20) /* Location Monitor 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define TSI148_LCSR_INTS_MB3S (1<<19) /* Mail Box 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define TSI148_LCSR_INTS_MB2S (1<<18) /* Mail Box 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define TSI148_LCSR_INTS_MB1S (1<<17) /* Mail Box 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define TSI148_LCSR_INTS_MB0S (1<<16) /* Mail Box 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define TSI148_LCSR_INTS_PERRS (1<<13) /* PCI/X Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define TSI148_LCSR_INTS_VERRS (1<<12) /* VMEbus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define TSI148_LCSR_INTS_VIES (1<<11) /* VMEbus IRQ Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define TSI148_LCSR_INTS_IACKS (1<<10) /* IACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define TSI148_LCSR_INTS_SYSFLS (1<<9) /* System Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define TSI148_LCSR_INTS_ACFLS (1<<8) /* AC Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define TSI148_LCSR_INTS_IRQ7S (1<<7) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define TSI148_LCSR_INTS_IRQ6S (1<<6) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define TSI148_LCSR_INTS_IRQ5S (1<<5) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define TSI148_LCSR_INTS_IRQ4S (1<<4) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define TSI148_LCSR_INTS_IRQ3S (1<<3) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define TSI148_LCSR_INTS_IRQ2S (1<<2) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define TSI148_LCSR_INTS_IRQ1S (1<<1) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) TSI148_LCSR_INTS_LM1S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) TSI148_LCSR_INTS_LM2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) TSI148_LCSR_INTS_LM3S };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) TSI148_LCSR_INTS_MB1S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) TSI148_LCSR_INTS_MB2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) TSI148_LCSR_INTS_MB3S };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * Interrupt Clear Register CRG + $44C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define TSI148_LCSR_INTC_DMA1C (1<<25) /* DMA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define TSI148_LCSR_INTC_DMA0C (1<<24) /* DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define TSI148_LCSR_INTC_LM3C (1<<23) /* Location Monitor 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define TSI148_LCSR_INTC_LM2C (1<<22) /* Location Monitor 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define TSI148_LCSR_INTC_LM1C (1<<21) /* Location Monitor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define TSI148_LCSR_INTC_LM0C (1<<20) /* Location Monitor 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define TSI148_LCSR_INTC_MB3C (1<<19) /* Mail Box 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define TSI148_LCSR_INTC_MB2C (1<<18) /* Mail Box 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define TSI148_LCSR_INTC_MB1C (1<<17) /* Mail Box 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define TSI148_LCSR_INTC_MB0C (1<<16) /* Mail Box 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define TSI148_LCSR_INTC_PERRC (1<<13) /* VMEbus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define TSI148_LCSR_INTC_VERRC (1<<12) /* VMEbus Access Time-out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define TSI148_LCSR_INTC_VIEC (1<<11) /* VMEbus IRQ Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define TSI148_LCSR_INTC_IACKC (1<<10) /* IACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define TSI148_LCSR_INTC_SYSFLC (1<<9) /* System Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define TSI148_LCSR_INTC_ACFLC (1<<8) /* AC Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) TSI148_LCSR_INTC_LM1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) TSI148_LCSR_INTC_LM2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) TSI148_LCSR_INTC_LM3C };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) TSI148_LCSR_INTC_MB1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) TSI148_LCSR_INTC_MB2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) TSI148_LCSR_INTC_MB3C };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Interrupt Map Register 1 CRG + $458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define TSI148_LCSR_INTM1_DMA1M_M (3<<18) /* DMA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define TSI148_LCSR_INTM1_DMA0M_M (3<<16) /* DMA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define TSI148_LCSR_INTM1_LM3M_M (3<<14) /* Location Monitor 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define TSI148_LCSR_INTM1_LM2M_M (3<<12) /* Location Monitor 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define TSI148_LCSR_INTM1_LM1M_M (3<<10) /* Location Monitor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define TSI148_LCSR_INTM1_LM0M_M (3<<8) /* Location Monitor 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define TSI148_LCSR_INTM1_MB3M_M (3<<6) /* Mail Box 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define TSI148_LCSR_INTM1_MB2M_M (3<<4) /* Mail Box 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define TSI148_LCSR_INTM1_MB1M_M (3<<2) /* Mail Box 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define TSI148_LCSR_INTM1_MB0M_M (3<<0) /* Mail Box 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * Interrupt Map Register 2 CRG + $45C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define TSI148_LCSR_INTM2_PERRM_M (3<<26) /* PCI Bus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define TSI148_LCSR_INTM2_VERRM_M (3<<24) /* VMEbus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define TSI148_LCSR_INTM2_VIEM_M (3<<22) /* VMEbus IRQ Edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define TSI148_LCSR_INTM2_IACKM_M (3<<20) /* IACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define TSI148_LCSR_INTM2_SYSFLM_M (3<<18) /* System Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define TSI148_LCSR_INTM2_ACFLM_M (3<<16) /* AC Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define TSI148_LCSR_INTM2_IRQ7M_M (3<<14) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define TSI148_LCSR_INTM2_IRQ6M_M (3<<12) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define TSI148_LCSR_INTM2_IRQ5M_M (3<<10) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define TSI148_LCSR_INTM2_IRQ4M_M (3<<8) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define TSI148_LCSR_INTM2_IRQ3M_M (3<<6) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define TSI148_LCSR_INTM2_IRQ2M_M (3<<4) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define TSI148_LCSR_INTM2_IRQ1M_M (3<<2) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * DMA Control (0-1) Registers CRG + $500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define TSI148_LCSR_DCTL_VBKS_1024 (5<<12) /* VMEbus block Size 1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define TSI148_LCSR_DCTL_VBKS_2048 (6<<12) /* VMEbus block Size 2048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define TSI148_LCSR_DCTL_VBKS_4096 (7<<12) /* VMEbus block Size 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define TSI148_LCSR_DCTL_PBKS_1024 (5<<4) /* PCI block size 1024 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define TSI148_LCSR_DCTL_PBKS_2048 (6<<4) /* PCI block size 2048 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define TSI148_LCSR_DCTL_PBKS_4096 (7<<4) /* PCI block size 4096 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * DMA Status Registers (0-1) CRG + $504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define TSI148_LCSR_DSTA_SMA (1<<31) /* PCI Signalled Master Abt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define TSI148_LCSR_DSTA_RTA (1<<30) /* PCI Received Target Abt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define TSI148_LCSR_DSTA_MRC (1<<29) /* PCI Max Retry Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define TSI148_LCSR_DSTA_VBE (1<<28) /* VMEbus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define TSI148_LCSR_DSTA_DON (1<<25) /* Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * DMA Current Link Address Lower (0-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * DMA Source Attribute (0-1) Reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define TSI148_LCSR_DSAT_NIN (1<<24) /* No Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define TSI148_LCSR_DSAT_AMODE_A16 (0<<0) /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define TSI148_LCSR_DSAT_AMODE_A24 (1<<0) /* A24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define TSI148_LCSR_DSAT_AMODE_A64 (4<<0) /* A64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0) /* User1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0) /* User2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0) /* User3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0) /* User4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * DMA Destination Attribute Registers (0-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define TSI148_LCSR_DDAT_AMODE_A16 (0<<0) /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define TSI148_LCSR_DDAT_AMODE_A24 (1<<0) /* A24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define TSI148_LCSR_DDAT_AMODE_A64 (4<<0) /* A64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0) /* User1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0) /* User2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0) /* User3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0) /* User4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * DMA Next Link Address Lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * DMA 2eSST Broadcast Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define TSI148_LCSR_DBS_M (0x1FFFFF<<0) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * GCSR Register Group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * GCSR Control and Status Register CRG + $604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * CR/CSR Register Group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * CR/CSR Bit Clear Register CRG + $FF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * CR/CSR Bit Set Register CRG+$FF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define TSI148_CRCSR_CSRBSR_LISTS (1<<7) /* Local Reset Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * CR/CSR Base Address Register CRG + FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define TSI148_CRCSR_CBAR_M (0x1F<<3) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #endif /* TSI148_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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