^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ca91c042.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the Tundra Universe 1 and Universe II VME bridge chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Tom Armistead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Updated by Ajit Prem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2004 Motorola Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Further updated by Martyn Welch <martyn.welch@ge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Derived from ca91c042.h by Michael Wyrick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef _CA91CX42_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _CA91CX42_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef PCI_VENDOR_ID_TUNDRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_VENDOR_ID_TUNDRA 0x10e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef PCI_DEVICE_ID_TUNDRA_CA91C142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Define the number of each that the CA91C142 supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CA91C142_MAX_MASTER 8 /* Max Master Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CA91C142_MAX_DMA 1 /* Max DMA Controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Structure used to hold driver specific information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ca91cx42_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *base; /* Base Address of device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) wait_queue_head_t dma_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) wait_queue_head_t iack_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) wait_queue_head_t mbox_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void (*lm_callback[4])(void *); /* Called in interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void *lm_data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void *crcsr_kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dma_addr_t crcsr_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mutex vme_rmw; /* Only one RMW cycle at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mutex vme_int; /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Only one VME interrupt can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * generated at a time, provide locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* See Page 2-77 in the Universe User Manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct ca91cx42_dma_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int dctl; /* DMA Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int dtbc; /* Transfer Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int dla; /* PCI Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int res1; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int dva; /* Vme Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int res2; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int res3; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ca91cx42_dma_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ca91cx42_dma_descriptor descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Universe Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* general PCI configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CA91CX42_PCI_ID 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CA91CX42_PCI_CSR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CA91CX42_PCI_CLASS 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CA91CX42_PCI_MISC0 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CA91CX42_PCI_BS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CA91CX42_PCI_MISC1 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LSI0_CTL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LSI0_BS 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LSI0_BD 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LSI0_TO 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LSI1_CTL 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LSI1_BS 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LSI1_BD 0x011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LSI1_TO 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LSI2_CTL 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LSI2_BS 0x012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LSI2_BD 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LSI2_TO 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LSI3_CTL 0x013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LSI3_BS 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LSI3_BD 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LSI3_TO 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LSI4_CTL 0x01A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LSI4_BS 0x01A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LSI4_BD 0x01A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LSI4_TO 0x01AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LSI5_CTL 0x01B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LSI5_BS 0x01B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LSI5_BD 0x01BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LSI5_TO 0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LSI6_CTL 0x01C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LSI6_BS 0x01CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LSI6_BD 0x01D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LSI6_TO 0x01D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LSI7_CTL 0x01DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LSI7_BS 0x01E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LSI7_BD 0x01E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LSI7_TO 0x01E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SCYC_CTL 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SCYC_ADDR 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SCYC_EN 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SCYC_CMP 0x017C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SCYC_SWP 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LMISC 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SLSI 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define L_CMDERR 0x018C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LAERR 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DCTL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DTBC 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DLA 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DVA 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DCPP 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DGCS 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define D_LLUE 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LINT_EN 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LINT_STAT 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LINT_MAP0 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LINT_MAP1 0x030C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VINT_EN 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VINT_STAT 0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VINT_MAP0 0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VINT_MAP1 0x031C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define STATID 0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define V1_STATID 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define V2_STATID 0x0328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define V3_STATID 0x032C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define V4_STATID 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define V5_STATID 0x0334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define V6_STATID 0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define V7_STATID 0x033C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) V4_STATID, V5_STATID, V6_STATID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) V7_STATID };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LINT_MAP2 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VINT_MAP2 0x0344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MBOX0 0x0348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MBOX1 0x034C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MBOX2 0x0350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MBOX3 0x0354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SEMA0 0x0358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SEMA1 0x035C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MAST_CTL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MISC_CTL 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MISC_STAT 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define USER_AM 0x040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VSI0_CTL 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VSI0_BS 0x0F04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VSI0_BD 0x0F08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define VSI0_TO 0x0F0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define VSI1_CTL 0x0F14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define VSI1_BS 0x0F18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define VSI1_BD 0x0F1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define VSI1_TO 0x0F20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define VSI2_CTL 0x0F28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define VSI2_BS 0x0F2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define VSI2_BD 0x0F30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define VSI2_TO 0x0F34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VSI3_CTL 0x0F3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define VSI3_BS 0x0F40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define VSI3_BD 0x0F44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define VSI3_TO 0x0F48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LM_CTL 0x0F64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LM_BS 0x0F68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define VRAI_CTL 0x0F70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define VRAI_BS 0x0F74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define VCSR_CTL 0x0F80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define VCSR_TO 0x0F84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define V_AMERR 0x0F88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define VAERR 0x0F8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define VSI4_CTL 0x0F90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define VSI4_BS 0x0F94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define VSI4_BD 0x0F98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define VSI4_TO 0x0F9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VSI5_CTL 0x0FA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VSI5_BS 0x0FA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VSI5_BD 0x0FAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VSI5_TO 0x0FB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VSI6_CTL 0x0FB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VSI6_BS 0x0FBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VSI6_BD 0x0FC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VSI6_TO 0x0FC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define VSI7_CTL 0x0FCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define VSI7_BS 0x0FD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VSI7_BD 0x0FD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VSI7_TO 0x0FD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VCSR_CLR 0x0FF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VCSR_SET 0x0FF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VCSR_BS 0x0FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * PCI Class Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * offset 008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CA91CX42_OF_PCI_CLASS_BASE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CA91CX42_OF_PCI_CLASS_SUB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CA91CX42_OF_PCI_CLASS_PROG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CA91CX42_BM_PCI_CLASS_RID 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CA91CX42_OF_PCI_CLASS_RID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * PCI Misc Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * offset 00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CA91CX42_OF_PCI_MISC0_LTIMER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * LSI Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * offset 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CA91CX42_LSI_CTL_EN (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CA91CX42_LSI_CTL_PWEN (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CA91CX42_LSI_CTL_VDW_M (3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CA91CX42_LSI_CTL_VDW_D8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CA91CX42_LSI_CTL_VDW_D16 (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CA91CX42_LSI_CTL_VDW_D32 (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CA91CX42_LSI_CTL_VDW_D64 (3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CA91CX42_LSI_CTL_VAS_M (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CA91CX42_LSI_CTL_VAS_A16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CA91CX42_LSI_CTL_VAS_A24 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CA91CX42_LSI_CTL_VAS_A32 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CA91CX42_LSI_CTL_VAS_USER1 (3<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CA91CX42_LSI_CTL_VAS_USER2 (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CA91CX42_LSI_CTL_PGM_M (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CA91CX42_LSI_CTL_PGM_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CA91CX42_LSI_CTL_PGM_PGM (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CA91CX42_LSI_CTL_SUPER_M (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CA91CX42_LSI_CTL_SUPER_NPRIV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CA91CX42_LSI_CTL_VCT_M (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CA91CX42_LSI_CTL_VCT_BLT (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CA91CX42_LSI_CTL_VCT_MBLT (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CA91CX42_LSI_CTL_LAS (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * SCYC_CTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * offset 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CA91CX42_SCYC_CTL_LAS_PCIMEM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CA91CX42_SCYC_CTL_CYC_M (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CA91CX42_SCYC_CTL_CYC_RMW (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * LMISC Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * offset 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CA91CX42_BM_LMISC_CRT 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CA91CX42_OF_LMISC_CRT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CA91CX42_BM_LMISC_CWT 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CA91CX42_OF_LMISC_CWT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * SLSI Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * offset 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CA91CX42_BM_SLSI_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CA91CX42_BM_SLSI_PWEN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CA91CX42_BM_SLSI_VDW 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CA91CX42_OF_SLSI_VDW 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CA91CX42_BM_SLSI_PGM 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CA91CX42_OF_SLSI_PGM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CA91CX42_BM_SLSI_SUPER 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CA91CX42_OF_SLSI_SUPER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CA91CX42_BM_SLSI_BS 0x000000F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CA91CX42_OF_SLSI_BS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CA91CX42_BM_SLSI_LAS 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CA91CX42_OF_SLSI_LAS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * DCTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * offset 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CA91CX42_DCTL_L2V (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CA91CX42_DCTL_VDW_M (3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CA91CX42_DCTL_VDW_D8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CA91CX42_DCTL_VDW_D16 (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CA91CX42_DCTL_VDW_D32 (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CA91CX42_DCTL_VDW_D64 (3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CA91CX42_DCTL_VAS_M (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CA91CX42_DCTL_VAS_A16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CA91CX42_DCTL_VAS_A24 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CA91CX42_DCTL_VAS_A32 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CA91CX42_DCTL_VAS_USER1 (3<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CA91CX42_DCTL_VAS_USER2 (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CA91CX42_DCTL_PGM_M (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CA91CX42_DCTL_PGM_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CA91CX42_DCTL_PGM_PGM (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CA91CX42_DCTL_SUPER_M (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CA91CX42_DCTL_SUPER_NPRIV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CA91CX42_DCTL_SUPER_SUPR (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CA91CX42_DCTL_VCT_M (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CA91CX42_DCTL_VCT_BLT (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CA91CX42_DCTL_LD64EN (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * DCPP Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * offset 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CA91CX42_DCPP_M 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CA91CX42_DCPP_NULL (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * DMA General Control/Status Register (DGCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * offset 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CA91CX42_DGCS_GO (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CA91CX42_DGCS_STOP_REQ (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CA91CX42_DGCS_HALT_REQ (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CA91CX42_DGCS_CHAIN (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CA91CX42_DGCS_VON_M (7<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CA91CX42_DGCS_VOFF_M (0xf<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CA91CX42_DGCS_ACT (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CA91CX42_DGCS_STOP (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CA91CX42_DGCS_HALT (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CA91CX42_DGCS_DONE (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CA91CX42_DGCS_LERR (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CA91CX42_DGCS_VERR (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CA91CX42_DGCS_PERR (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CA91CX42_DGCS_INT_STOP (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CA91CX42_DGCS_INT_HALT (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CA91CX42_DGCS_INT_DONE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CA91CX42_DGCS_INT_LERR (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CA91CX42_DGCS_INT_VERR (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CA91CX42_DGCS_INT_PERR (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * PCI Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * offset 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CA91CX42_LINT_LM3 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CA91CX42_LINT_LM2 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CA91CX42_LINT_LM1 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CA91CX42_LINT_LM0 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CA91CX42_LINT_MBOX3 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CA91CX42_LINT_MBOX2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CA91CX42_LINT_MBOX1 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CA91CX42_LINT_MBOX0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CA91CX42_LINT_ACFAIL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CA91CX42_LINT_SYSFAIL 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CA91CX42_LINT_SW_INT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CA91CX42_LINT_SW_IACK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CA91CX42_LINT_VERR 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CA91CX42_LINT_LERR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CA91CX42_LINT_DMA 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CA91CX42_LINT_VIRQ7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CA91CX42_LINT_VIRQ6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CA91CX42_LINT_VIRQ5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CA91CX42_LINT_VIRQ4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CA91CX42_LINT_VIRQ3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CA91CX42_LINT_VIRQ2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CA91CX42_LINT_VIRQ1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CA91CX42_LINT_VOWN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CA91CX42_LINT_MBOX 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * MAST_CTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * offset 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CA91CX42_OF_MAST_CTL_MAXRTRY 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CA91CX42_BM_MAST_CTL_PWON 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CA91CX42_OF_MAST_CTL_PWON 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CA91CX42_BM_MAST_CTL_VRL 0x00C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CA91CX42_OF_MAST_CTL_VRL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CA91CX42_BM_MAST_CTL_VRM 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CA91CX42_BM_MAST_CTL_VREL 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CA91CX42_BM_MAST_CTL_VOWN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define CA91CX42_BM_MAST_CTL_PABS 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define CA91CX42_OF_MAST_CTL_BUS_NO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * MISC_CTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * offset 404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define CA91CX42_MISC_CTL_VBTO 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define CA91CX42_MISC_CTL_VARB 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define CA91CX42_MISC_CTL_VARBTO 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define CA91CX42_MISC_CTL_SW_LRST 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define CA91CX42_MISC_CTL_SW_SRST 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define CA91CX42_MISC_CTL_BI 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define CA91CX42_MISC_CTL_ENGBI 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define CA91CX42_MISC_CTL_RESCIND 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define CA91CX42_MISC_CTL_SYSCON 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define CA91CX42_MISC_CTL_V64AUTO 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CA91CX42_OF_MISC_CTL_VARBTO 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define CA91CX42_OF_MISC_CTL_VBTO 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * MISC_STAT Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * offset 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define CA91CX42_BM_MISC_STAT_TXFE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define CA91CX42_BM_MISC_STAT_RXFE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CA91CX42_OF_MISC_STAT_DY4AUTOID 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * VSI Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * offset F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define CA91CX42_VSI_CTL_EN (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define CA91CX42_VSI_CTL_PWEN (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CA91CX42_VSI_CTL_PREN (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CA91CX42_VSI_CTL_PGM_M (3<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CA91CX42_VSI_CTL_PGM_DATA (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CA91CX42_VSI_CTL_PGM_PGM (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define CA91CX42_VSI_CTL_SUPER_M (3<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define CA91CX42_VSI_CTL_VAS_M (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define CA91CX42_VSI_CTL_VAS_A16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define CA91CX42_VSI_CTL_VAS_A24 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define CA91CX42_VSI_CTL_VAS_A32 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define CA91CX42_VSI_CTL_VAS_USER1 (3<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define CA91CX42_VSI_CTL_VAS_USER2 (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define CA91CX42_VSI_CTL_LD64EN (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define CA91CX42_VSI_CTL_LLRMW (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define CA91CX42_VSI_CTL_LAS_M (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define CA91CX42_VSI_CTL_LAS_PCI_MS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* LM_CTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * offset F64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define CA91CX42_LM_CTL_EN (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define CA91CX42_LM_CTL_PGM (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define CA91CX42_LM_CTL_DATA (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define CA91CX42_LM_CTL_SUPR (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define CA91CX42_LM_CTL_NPRIV (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define CA91CX42_LM_CTL_AS_M (7<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define CA91CX42_LM_CTL_AS_A16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define CA91CX42_LM_CTL_AS_A24 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define CA91CX42_LM_CTL_AS_A32 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * VRAI_CTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * offset F70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define CA91CX42_BM_VRAI_CTL_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define CA91CX42_OF_VRAI_CTL_PGM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define CA91CX42_OF_VRAI_CTL_SUPER 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define CA91CX42_BM_VRAI_CTL_VAS 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define CA91CX42_OF_VRAI_CTL_VAS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* VCSR_CTL Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * offset F80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define CA91CX42_VCSR_CTL_EN (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define CA91CX42_VCSR_CTL_LAS_M (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define CA91CX42_VCSR_CTL_LAS_PCI_MS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* VCSR_BS Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * offset FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #endif /* _CA91CX42_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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