^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/vgastate.c -- VGA state save/restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2002 James Simmons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright history from vga16fb.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 1999 Ben Pfaff and Petr Vandrovec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on VESA framebuffer (c) 1998 Gerd Knorr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct regstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) __u8 *vga_font0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __u8 *vga_font1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __u8 *vga_text;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __u8 *vga_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __u8 *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __u8 *crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __u8 *gfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __u8 *seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __u8 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline unsigned char vga_rcrtcs(void __iomem *regbase, unsigned short iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) vga_w(regbase, iobase + 0x4, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return vga_r(regbase, iobase + 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void vga_wcrtcs(void __iomem *regbase, unsigned short iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) vga_w(regbase, iobase + 0x4, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) vga_w(regbase, iobase + 0x5, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void save_vga_text(struct vgastate *state, void __iomem *fbbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 misc, attr10, gr4, gr5, gr6, seq1, seq2, seq4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned short iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* if in graphics mode, no need to save */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) misc = vga_r(state->vgabase, VGA_MIS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) iobase = (misc & 1) ? 0x3d0 : 0x3b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) vga_w(state->vgabase, VGA_ATT_W, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) attr10 = vga_rattr(state->vgabase, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) vga_w(state->vgabase, VGA_ATT_W, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (attr10 & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* save regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* blank screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 | 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* save font at plane 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (state->flags & VGA_SAVE_FONT0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) for (i = 0; i < 4 * 8192; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) saved->vga_font0[i] = vga_r(fbbase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* save font at plane 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (state->flags & VGA_SAVE_FONT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (i = 0; i < state->memsize; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) saved->vga_font1[i] = vga_r(fbbase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* save font at plane 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (state->flags & VGA_SAVE_TEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (i = 0; i < 8192; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) saved->vga_text[i] = vga_r(fbbase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (i = 0; i < 8192; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) saved->vga_text[8192+i] = vga_r(fbbase + 2 * 8192, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* restore regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* unblank screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 & ~(1 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void restore_vga_text(struct vgastate *state, void __iomem *fbbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 gr1, gr3, gr4, gr5, gr6, gr8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 seq1, seq2, seq4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* save regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) gr1 = vga_rgfx(state->vgabase, VGA_GFX_SR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) gr3 = vga_rgfx(state->vgabase, VGA_GFX_DATA_ROTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) gr4 = vga_rgfx(state->vgabase, VGA_GFX_PLANE_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) gr5 = vga_rgfx(state->vgabase, VGA_GFX_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) gr6 = vga_rgfx(state->vgabase, VGA_GFX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) gr8 = vga_rgfx(state->vgabase, VGA_GFX_BIT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) seq2 = vga_rseq(state->vgabase, VGA_SEQ_PLANE_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) seq4 = vga_rseq(state->vgabase, VGA_SEQ_MEMORY_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* blank screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) seq1 = vga_rseq(state->vgabase, VGA_SEQ_CLOCK_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 | 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (state->depth == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) vga_wgfx(state->vgabase, VGA_GFX_BIT_MASK, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* restore font at plane 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (state->flags & VGA_SAVE_FONT0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0; i < 4 * 8192; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) vga_w(fbbase, i, saved->vga_font0[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* restore font at plane 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (state->flags & VGA_SAVE_FONT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < state->memsize; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) vga_w(fbbase, i, saved->vga_font1[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* restore font at plane 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (state->flags & VGA_SAVE_TEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (i = 0; i < 8192; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) vga_w(fbbase, i, saved->vga_text[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < 8192; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) vga_w(fbbase, i, saved->vga_text[8192+i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* unblank screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1 & ~(1 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* restore regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) vga_wgfx(state->vgabase, VGA_GFX_SR_ENABLE, gr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) vga_wgfx(state->vgabase, VGA_GFX_DATA_ROTATE, gr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) vga_wgfx(state->vgabase, VGA_GFX_PLANE_READ, gr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) vga_wgfx(state->vgabase, VGA_GFX_MODE, gr5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) vga_wgfx(state->vgabase, VGA_GFX_MISC, gr6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) vga_wgfx(state->vgabase, VGA_GFX_BIT_MASK, gr8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, seq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) vga_wseq(state->vgabase, VGA_SEQ_PLANE_WRITE, seq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vga_wseq(state->vgabase, VGA_SEQ_MEMORY_MODE, seq4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void save_vga_mode(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned short iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) saved->misc = vga_r(state->vgabase, VGA_MIS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (saved->misc & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) iobase = 0x3d0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) iobase = 0x3b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) for (i = 0; i < state->num_crtc; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) saved->crtc[i] = vga_rcrtcs(state->vgabase, iobase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vga_w(state->vgabase, VGA_ATT_W, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0; i < state->num_attr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) saved->attr[i] = vga_rattr(state->vgabase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) vga_w(state->vgabase, VGA_ATT_W, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (i = 0; i < state->num_gfx; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) saved->gfx[i] = vga_rgfx(state->vgabase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (i = 0; i < state->num_seq; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) saved->seq[i] = vga_rseq(state->vgabase, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void restore_vga_mode(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned short iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) vga_w(state->vgabase, VGA_MIS_W, saved->misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (saved->misc & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) iobase = 0x3d0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iobase = 0x3b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* turn off display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) saved->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* disable sequencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* enable palette addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) vga_w(state->vgabase, VGA_ATT_W, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 2; i < state->num_seq; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) vga_wseq(state->vgabase, i, saved->seq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* unprotect vga regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) vga_wcrtcs(state->vgabase, iobase, 17, saved->crtc[17] & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < state->num_crtc; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) vga_wcrtcs(state->vgabase, iobase, i, saved->crtc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 0; i < state->num_gfx; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) vga_wgfx(state->vgabase, i, saved->gfx[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 0; i < state->num_attr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) vga_wattr(state->vgabase, i, saved->attr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* reenable sequencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* turn display on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) saved->seq[VGA_SEQ_CLOCK_MODE] & ~(1 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* disable video/palette source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) vga_r(state->vgabase, iobase + 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) vga_w(state->vgabase, VGA_ATT_W, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void save_vga_cmap(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) vga_w(state->vgabase, VGA_PEL_MSK, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* assumes DAC is readable and writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) vga_w(state->vgabase, VGA_PEL_IR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = 0; i < 768; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) saved->vga_cmap[i] = vga_r(state->vgabase, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void restore_vga_cmap(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) vga_w(state->vgabase, VGA_PEL_MSK, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* assumes DAC is readable and writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) vga_w(state->vgabase, VGA_PEL_IW, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (i = 0; i < 768; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) vga_w(state->vgabase, VGA_PEL_D, saved->vga_cmap[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void vga_cleanup(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (state->vidstate != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct regstate *saved = (struct regstate *) state->vidstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) vfree(saved->vga_font0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vfree(saved->vga_font1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) vfree(saved->vga_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) vfree(saved->vga_cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) vfree(saved->attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) kfree(saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) state->vidstate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int save_vga(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct regstate *saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) saved = kzalloc(sizeof(struct regstate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (saved == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) state->vidstate = (void *)saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (state->flags & VGA_SAVE_CMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) saved->vga_cmap = vmalloc(768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!saved->vga_cmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) save_vga_cmap(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (state->flags & VGA_SAVE_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (state->num_attr < 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) state->num_attr = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (state->num_crtc < 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) state->num_crtc = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (state->num_gfx < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) state->num_gfx = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (state->num_seq < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) state->num_seq = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) total = state->num_attr + state->num_crtc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) state->num_gfx + state->num_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) saved->attr = vmalloc(total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!saved->attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) saved->crtc = saved->attr + state->num_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) saved->gfx = saved->crtc + state->num_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) saved->seq = saved->gfx + state->num_gfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) save_vga_mode(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (state->flags & VGA_SAVE_FONTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void __iomem *fbbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* exit if window is less than 32K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (state->memsize && state->memsize < 4 * 8192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!state->memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) state->memsize = 8 * 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!state->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) state->membase = 0xA0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) fbbase = ioremap(state->membase, state->memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!fbbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * save only first 32K used by vgacon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (state->flags & VGA_SAVE_FONT0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) saved->vga_font0 = vmalloc(4 * 8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!saved->vga_font0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) iounmap(fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * largely unused, but if required by the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * we'll just save everything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (state->flags & VGA_SAVE_FONT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) saved->vga_font1 = vmalloc(state->memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!saved->vga_font1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) iounmap(fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Save 8K at plane0[0], and 8K at plane1[16K]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (state->flags & VGA_SAVE_TEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) saved->vga_text = vmalloc(8192 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!saved->vga_text) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) iounmap(fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) save_vga_text(state, fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) iounmap(fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int restore_vga(struct vgastate *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (state->vidstate == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (state->flags & VGA_SAVE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) restore_vga_mode(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (state->flags & VGA_SAVE_FONTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void __iomem *fbbase = ioremap(state->membase, state->memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!fbbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) restore_vga_text(state, fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iounmap(fbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (state->flags & VGA_SAVE_CMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) restore_vga_cmap(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) vga_cleanup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) EXPORT_SYMBOL(save_vga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) EXPORT_SYMBOL(restore_vga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MODULE_AUTHOR("James Simmons <jsimmons@users.sf.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MODULE_DESCRIPTION("VGA State Save/Restore");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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