^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _RGA_DRIVER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _RGA_DRIVER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dma-buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RGA_BLIT_SYNC 0x5017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RGA_BLIT_ASYNC 0x5018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RGA_FLUSH 0x5019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RGA_GET_RESULT 0x501a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RGA_GET_VERSION 0x501b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RGA_CACHE_FLUSH 0x501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RGA2_BLIT_SYNC 0x6017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RGA2_BLIT_ASYNC 0x6018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RGA2_FLUSH 0x6019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RGA2_GET_RESULT 0x601a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RGA2_GET_VERSION 0x601b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RGA2_REG_CTRL_LEN 0x8 /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RGA2_REG_CMD_LEN 0x20 /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RGA2_CMD_BUF_SIZE 0x700 /* 16*28*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RGA2_OUT_OF_RESOURCES -10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RGA2_MALLOC_ERROR -11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCALE_DOWN_LARGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define rgaIS_ERROR(status) (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define rgaNO_ERROR(status) (status >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define rgaIS_SUCCESS(status) (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RGA_BUF_GEM_TYPE_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RGA_BUF_GEM_TYPE_DMA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RGA2_MAJOR_VERSION_MASK (0xFF000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RGA2_MINOR_VERSION_MASK (0x00F00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RGA2_SVN_VERSION_MASK (0x000FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* RGA2 process mode enum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bitblt_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) color_palette_mode = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) color_fill_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) update_palette_table_mode = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) update_patten_buff_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }; /*render mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) A_B_B =0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) A_B_C =0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }; //bitblt_mode select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) rop_enable_mask = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dither_enable_mask = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) fading_enable_mask = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PD_enbale_mask = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) // Alpha Red Green Blue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 2, 16, {{ 0, 0, 5, 0 11, 5, 16,11}}, GGL_BGR }, // RK_FORMAT_BGR_565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 2, 16, {{ 1, 0, 6, 1, 11, 6, 16,11}}, GGL_BGRA }, // RK_FORMAT_BGRA_5551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 2, 16, {{ 4, 0, 8, 4, 12, 8, 16,12}}, GGL_BGRA }, // RK_FORMAT_BGRA_4444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RGA2_FORMAT_RGBA_8888 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RGA2_FORMAT_RGBX_8888 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RGA2_FORMAT_RGB_888 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RGA2_FORMAT_BGRA_8888 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RGA2_FORMAT_BGRX_8888 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RGA2_FORMAT_BGR_888 = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RGA2_FORMAT_RGB_565 = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RGA2_FORMAT_RGBA_5551 = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RGA2_FORMAT_RGBA_4444 = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RGA2_FORMAT_BGR_565 = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RGA2_FORMAT_BGRA_5551 = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RGA2_FORMAT_BGRA_4444 = 0xb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RGA2_FORMAT_Y4 = 0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RGA2_FORMAT_YCbCr_400 = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RGA2_FORMAT_YCbCr_422_SP = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RGA2_FORMAT_YCbCr_422_P = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RGA2_FORMAT_YCbCr_420_SP = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RGA2_FORMAT_YCbCr_420_P = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RGA2_FORMAT_YCrCb_422_SP = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RGA2_FORMAT_YCrCb_422_P = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RGA2_FORMAT_YCrCb_420_SP = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RGA2_FORMAT_YCrCb_420_P = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RGA2_FORMAT_YVYU_422 = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RGA2_FORMAT_YVYU_420 = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RGA2_FORMAT_VYUY_422 = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RGA2_FORMAT_VYUY_420 = 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RGA2_FORMAT_YUYV_422 = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RGA2_FORMAT_YUYV_420 = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RGA2_FORMAT_UYVY_422 = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RGA2_FORMAT_UYVY_420 = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RGA2_FORMAT_YCbCr_420_SP_10B = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RGA2_FORMAT_YCrCb_420_SP_10B = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RGA2_FORMAT_YCbCr_422_SP_10B = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RGA2_FORMAT_YCrCb_422_SP_10B = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) RGA2_FORMAT_BPP_1 = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RGA2_FORMAT_BPP_2 = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) RGA2_FORMAT_BPP_4 = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) RGA2_FORMAT_BPP_8 = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RGA2_FORMAT_ARGB_8888 = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RGA2_FORMAT_XRGB_8888 = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RGA2_FORMAT_ARGB_5551 = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) RGA2_FORMAT_ARGB_4444 = 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RGA2_FORMAT_ABGR_8888 = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) RGA2_FORMAT_XBGR_8888 = 0x2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) RGA2_FORMAT_ABGR_5551 = 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) RGA2_FORMAT_ABGR_4444 = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) typedef struct mdp_img
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mdp_img;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) typedef struct mdp_img_act
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 width; // width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 height; // height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) s16 x_off; // x offset for the vir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) s16 y_off; // y offset for the vir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) s16 uv_x_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) s16 uv_y_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mdp_img_act;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) typedef struct mdp_img_vir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 uv_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 v_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mdp_img_vir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) typedef struct MMU_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long src0_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long src1_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long dst_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long els_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 src0_mmu_flag; /* [0] src0 mmu enable [1] src0_flush [2] src0_prefetch_en [3] src0_prefetch dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 dst_mmu_flag; /* [0] dst mmu enable [1] dst_flush [2] dst_prefetch_en [3] dst_prefetch dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 els_mmu_flag; /* [0] els mmu enable [1] els_flush [2] els_prefetch_en [3] els_prefetch dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } MMU_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MMU_DIS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MMU_EN = 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MMU_FLUSH_DIS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MMU_FLUSH_EN = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MMU_PRE_DIS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MMU_PRE_EN = 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MMU_PRE_DIR_FORW = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MMU_PRE_DIR_BACK = 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) typedef struct COLOR_FILL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) s16 gr_x_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) s16 gr_y_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) s16 gr_x_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) s16 gr_y_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) s16 gr_x_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) s16 gr_y_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) s16 gr_x_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) s16 gr_y_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) COLOR_FILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ALPHA_ORIGINAL = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ALPHA_NO_128 = 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) R2_BLACK = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) R2_COPYPEN = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) R2_MASKNOTPEN = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) R2_MASKPEN = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) R2_MASKPENNOT = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) R2_MERGENOTPEN = 0xaf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) R2_MERGEPEN = 0xfa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) R2_MERGEPENNOT = 0xf5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) R2_NOP = 0xaa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) R2_NOT = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) R2_NOTCOPYPEN = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) R2_NOTMASKPEN = 0x5f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) R2_NOTMERGEPEN = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) R2_NOTXORPEN = 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) R2_WHITE = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) R2_XORPEN = 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* porting from rga.h for msg convert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) typedef struct FADING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint8_t b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) uint8_t g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint8_t r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint8_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FADING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) typedef struct MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned char mmu_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } MMU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) typedef struct MMU_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned char mmu_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) uint32_t base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } MMU_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) typedef struct RECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned short xmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned short xmax; // width - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned short ymin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned short ymax; // height - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } RECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) typedef struct POINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned short x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned short y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) POINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) typedef struct line_draw_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) POINT start_point; /* LineDraw_start_point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) POINT end_point; /* LineDraw_end_point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint32_t color; /* LineDraw_color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint32_t flag; /* (enum) LineDrawing mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint32_t line_width; /* range 1~16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) line_draw_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* color space convert coefficient. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) typedef struct csc_coe_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int16_t r_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int16_t g_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int16_t b_u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int32_t off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } csc_coe_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) typedef struct full_csc_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) csc_coe_t coe_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) csc_coe_t coe_u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) csc_coe_t coe_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } full_csc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) typedef struct rga_img_info_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned long yrgb_addr; /* yrgb mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long uv_addr; /* cb/cr mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long v_addr; /* cr mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int format; //definition by RK_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned short act_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned short act_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned short x_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned short y_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned short vir_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned short vir_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned short endian_mode; //for BPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned short alpha_swap; /* not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rga_img_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) typedef struct rga_img_info_32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uint32_t yrgb_addr; /* yrgb mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) uint32_t uv_addr; /* cb/cr mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uint32_t v_addr; /* cr mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int format; //definition by RK_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned short act_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned short act_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned short x_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned short y_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned short vir_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned short vir_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned short endian_mode; //for BPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned short alpha_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rga_img_info_32_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct rga_dma_buffer_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* DMABUF information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct dma_buf *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct dma_buf_attachment *attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dma_addr_t iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct rga_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint8_t render_mode; /* (enum) process mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rga_img_info_t src; /* src image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rga_img_info_t dst; /* dst image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rga_img_info_t pat; /* patten image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long rop_mask_addr; /* rop4 mask addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned long LUT_addr; /* LUT addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RECT clip; /* dst clip window default value is dst_vir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* value from [0, w-1] / [0, h-1]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int32_t sina; /* dst angle default value 0 16.16 scan from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int32_t cosa; /* dst angle default value 0 16.16 scan from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) uint16_t alpha_rop_flag; /* alpha rop process flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* ([0] = 1 alpha_rop_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* ([1] = 1 rop enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* ([2] = 1 fading_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* ([3] = 1 PD_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* ([4] = 1 alpha cal_mode_sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* ([5] = 1 dither_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* ([6] = 1 gradient fill mode sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* ([7] = 1 AA_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint32_t color_key_max; /* color key max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uint32_t color_key_min; /* color key min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) uint32_t fg_color; /* foreground color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uint32_t bg_color; /* background color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) COLOR_FILL gr_color; /* color fill use gradient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) line_draw_t line_draw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FADING fading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint8_t PD_mode; /* porter duff alpha mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint8_t alpha_global_value; /* global alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uint8_t endian_mode; /* 0/big endian 1/little endian*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) uint8_t rotate_mode; /* (enum) rotate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* 0x0, no rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* 0x1, rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* 0x2, x_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* 0x3, y_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MMU mmu_info; /* mmu information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* ([2~3] rop mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* ([4] zero mode en) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* ([5] dst alpha mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* ([6] alpha output mode sel) 0 src / 1 dst*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) uint8_t src_trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uint8_t dither_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) full_csc_t full_csc; /* full color space convert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct rga_req_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uint8_t render_mode; /* (enum) process mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rga_img_info_32_t src; /* src image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rga_img_info_32_t dst; /* dst image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rga_img_info_32_t pat; /* patten image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) uint32_t rop_mask_addr; /* rop4 mask addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) uint32_t LUT_addr; /* LUT addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) RECT clip; /* dst clip window default value is dst_vir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* value from [0, w-1] / [0, h-1]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int32_t sina; /* dst angle default value 0 16.16 scan from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int32_t cosa; /* dst angle default value 0 16.16 scan from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) uint16_t alpha_rop_flag; /* alpha rop process flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* ([0] = 1 alpha_rop_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* ([1] = 1 rop enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* ([2] = 1 fading_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* ([3] = 1 PD_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* ([4] = 1 alpha cal_mode_sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* ([5] = 1 dither_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* ([6] = 1 gradient fill mode sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* ([7] = 1 AA_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint32_t color_key_max; /* color key max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uint32_t color_key_min; /* color key min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) uint32_t fg_color; /* foreground color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uint32_t bg_color; /* background color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) COLOR_FILL gr_color; /* color fill use gradient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) line_draw_t line_draw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) FADING fading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint8_t PD_mode; /* porter duff alpha mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t alpha_global_value; /* global alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint8_t endian_mode; /* 0/big endian 1/little endian*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint8_t rotate_mode; /* (enum) rotate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* 0x0, no rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* 0x1, rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* 0x2, x_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* 0x3, y_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MMU_32 mmu_info; /* mmu information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* ([2~3] rop mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* ([4] zero mode en) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* ([5] dst alpha mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* ([6] alpha output mode sel) 0 src / 1 dst*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint8_t src_trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t dither_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) full_csc_t full_csc; /* full color space convert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct rga2_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 render_mode; /* (enum) process mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rga_img_info_t src; // src active window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rga_img_info_t src1; // src1 active window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rga_img_info_t dst; // dst active window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rga_img_info_t pat; // patten active window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long rop_mask_addr; // rop4 mask addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned long LUT_addr; // LUT addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 rop_mask_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u8 bitblt_mode; /* 0: SRC + DST => DST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* 1: SRC + SRC1 => DST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 rotate_mode; /* [1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* 0 degree 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* 90 degree 0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* 180 degree 0x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* 270 degree 0x3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* [5:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* none 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* x_mirror 0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* y_mirror 0x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* x_mirror + y_mirror 0x3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u16 alpha_rop_flag; /* alpha rop process flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* ([0] = 1 alpha_rop_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* ([1] = 1 rop enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* ([2] = 1 fading_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* ([3] = 1 alpha cal_mode_sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* ([4] = 1 src_dither_up_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* ([5] = 1 dst_dither_up_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* ([6] = 1 dither_down_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* ([7] = 1 gradient fill mode sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u16 alpha_mode_0; /* [0] SrcAlphaMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* [2:1] SrcGlobalAlphaMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* [3] SrcAlphaSelectMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* [6:4] SrcFactorMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* [7] SrcColorMode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* [8] DstAlphaMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* [10:9] DstGlobalAlphaMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* [11] DstAlphaSelectMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* [14:12] DstFactorMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* [15] DstColorMode0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u16 alpha_mode_1; /* [0] SrcAlphaMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* [2:1] SrcGlobalAlphaMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* [3] SrcAlphaSelectMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* [6:4] SrcFactorMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* [8] DstAlphaMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* [10:9] DstGlobalAlphaMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* [11] DstAlphaSelectMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* [14:12] DstFactorMode1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 scale_bicu_mode; /* 0 1 2 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 color_key_max; /* color key max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 color_key_min; /* color key min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 fg_color; /* foreground color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 bg_color; /* background color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 color_fill_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) COLOR_FILL gr_color; /* color fill use gradient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 fading_alpha_value; /* Fading value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 fading_r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 fading_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 fading_b_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 src_a_global_val; /* src global alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 dst_a_global_val; /* dst global alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u8 rop_mode; /* rop mode select 0 : rop2 1 : rop3 2 : rop4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u16 rop_code; /* rop2/3/4 code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* [1:0] src0 csc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* [3:2] dst csc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* [4] dst csc clip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* [6:5] src1 csc mdoe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* [7] src1 csc clip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) full_csc_t full_csc; /* full color space convert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 endian_mode; /* 0/little endian 1/big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 CMD_fin_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MMU_INFO mmu_info; /* mmu infomation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u8 alpha_zero_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 src_trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u8 alpha_swp; /* not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 dither_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u8 rgb2yuv_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct rga2_mmu_buf_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int32_t front;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int32_t back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int32_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int32_t curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int *buf_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 buf_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u8 pages_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) BB_ROTATE_OFF = 0x0, /* no rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) BB_ROTATE_90 = 0x1, /* rotate 90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) BB_ROTATE_180 = 0x2, /* rotate 180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) BB_ROTATE_270 = 0x3, /* rotate 270 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }; /*rotate mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) BB_MIRROR_OFF = (0x0 << 4), /* no mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) BB_MIRROR_X = (0x1 << 4), /* x mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) BB_MIRROR_Y = (0x2 << 4), /* y mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) BB_MIRROR_XY = (0x3 << 4), /* xy mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }; /*mirror mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) BB_COPY_USE_TILE = (0x1 << 6), /* bitblt mode copy but use Tile mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) //BYPASS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) BT_601_RANGE0 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) BT_601_RANGE1 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) BT_709_RANGE0 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }; /*yuv2rgb_mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) BPP1 = 0x0, /* BPP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) BPP2 = 0x1, /* BPP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) BPP4 = 0x2, /* BPP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) BPP8 = 0x3 /* BPP8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }; /*palette_mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SOLID_COLOR = 0x0, //color fill mode; ROP4: SOLID_rop4_mask_addr COLOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PATTERN_COLOR = 0x1 //pattern_fill_mode;ROP4:PATTERN_COLOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }; /*color fill mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) COLOR_FILL_CLIP = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) COLOR_FILL_NOT_CLIP = 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) CATROM = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MITCHELL = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) HERMITE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) B_SPLINE = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }; /*bicubic coefficient*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ROP2 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ROP3 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ROP4 = 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }; /*ROP mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) BIG_ENDIAN = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) LITTLE_ENDIAN = 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }; /*endian mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MMU_TABLE_4KB = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MMU_TABLE_64KB = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }; /*MMU table size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RGB_2_666 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RGB_2_565 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RGB_2_555 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RGB_2_444 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }; /*dither down mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * struct for process session which connect to rga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @author ZhangShengqin (2012-2-15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) typedef struct rga2_session {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* a linked list of data so we can access them for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct list_head list_session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* a linked list of register data waiting for process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct list_head waiting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* a linked list of register data in processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct list_head running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* all coommand this thread done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) atomic_t done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pid_t pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) atomic_t task_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) atomic_t num_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) } rga2_session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct rga2_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rga2_session *session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct list_head session_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct list_head status_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) uint32_t sys_reg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) uint32_t csc_reg[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uint32_t cmd_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) uint32_t *MMU_src0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uint32_t *MMU_src1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint32_t *MMU_dst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) uint32_t MMU_src0_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) uint32_t MMU_src1_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) uint32_t MMU_dst_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) uint32_t MMU_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) bool MMU_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct rga_dma_buffer_t dma_buffer_src0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct rga_dma_buffer_t dma_buffer_src1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct rga_dma_buffer_t dma_buffer_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct rga_dma_buffer_t dma_buffer_els;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct rga2_service_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct timer_list timer; /* timer for power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct list_head waiting; /* link to link_reg in struct vpu_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct list_head running; /* link to link_reg in struct vpu_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct list_head done; /* link to link_reg in struct vpu_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct list_head session; /* link to list_session in struct vpu_session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) atomic_t total_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct rga2_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) uint32_t cmd_buff[32*8];/* cmd_buff for rga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint32_t *pre_scale_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) atomic_t int_disable; /* 0 int enable 1 int disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) atomic_t cmd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) atomic_t src_format_swt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int last_prc_src_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) atomic_t rga_working;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) uint32_t dev_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) //struct rga_req req[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct mutex mutex; // mutex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define RGA2_TEST_CASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) //General Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define RGA2_SYS_CTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define RGA2_CMD_CTRL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define RGA2_CMD_BASE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define RGA2_STATUS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define RGA2_INT 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define RGA2_MMU_CTRL0 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define RGA2_MMU_CMD_BASE 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) //Full Csc Coefficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define RGA2_CSC_COE_BASE 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) //Command code start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define RGA2_MODE_CTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define RGA_BLIT_COMPLETE_EVENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #endif /*_RK29_IPP_DRIVER_H_*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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