^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _RGA_DRIVER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _RGA_DRIVER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RGA_BLIT_SYNC 0x5017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RGA_BLIT_ASYNC 0x5018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RGA_FLUSH 0x5019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RGA_GET_RESULT 0x501a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RGA_GET_VERSION 0x501b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RGA_REG_CTRL_LEN 0x8 /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RGA_REG_CMD_LEN 0x20 /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RGA_OUT_OF_RESOURCES -10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RGA_MALLOC_ERROR -11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RGA_BUF_GEM_TYPE_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define rgaIS_ERROR(status) (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define rgaNO_ERROR(status) (status >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define rgaIS_SUCCESS(status) (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RGA_DEBUGFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* RGA process mode enum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bitblt_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) color_palette_mode = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) color_fill_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) line_point_drawing_mode = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) blur_sharp_filter_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pre_scaling_mode = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) update_palette_table_mode = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) update_patten_buff_mode = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rop_enable_mask = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dither_enable_mask = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) fading_enable_mask = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PD_enbale_mask = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) yuv2rgb_mode2 = 0x2, /* BT.709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* RGA rotate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rotate_mode0 = 0x0, /* no rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rotate_mode1 = 0x1, /* rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) rotate_mode2 = 0x2, /* x_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) rotate_mode3 = 0x3, /* y_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) color_palette_mode0 = 0x0, /* 1K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) color_palette_mode1 = 0x1, /* 2K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) color_palette_mode2 = 0x2, /* 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) color_palette_mode3 = 0x3, /* 8K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) // Alpha Red Green Blue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RK_FORMAT_RGBA_8888 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK_FORMAT_RGBX_8888 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK_FORMAT_RGB_888 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RK_FORMAT_BGRA_8888 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RK_FORMAT_RGB_565 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RK_FORMAT_RGBA_5551 = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RK_FORMAT_RGBA_4444 = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK_FORMAT_BGR_888 = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK_FORMAT_YCbCr_422_SP = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK_FORMAT_YCbCr_422_P = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RK_FORMAT_YCbCr_420_SP = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RK_FORMAT_YCbCr_420_P = 0xb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RK_FORMAT_YCrCb_422_SP = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RK_FORMAT_YCrCb_422_P = 0xd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RK_FORMAT_YCrCb_420_SP = 0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RK_FORMAT_YCrCb_420_P = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK_FORMAT_BPP1 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK_FORMAT_BPP2 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK_FORMAT_BPP4 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RK_FORMAT_BPP8 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK_FORMAT_YCbCr_420_SP_10B = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RK_FORMAT_YCrCb_420_SP_10B = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) typedef struct rga_img_info_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long yrgb_addr; /* yrgb mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long uv_addr; /* cb/cr mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long v_addr; /* cr mem addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int format; //definition by RK_FORMAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned short act_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned short act_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned short x_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned short y_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned short vir_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned short vir_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned short endian_mode; //for BPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned short alpha_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rga_img_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) typedef struct mdp_img_act
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned short w; // width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned short h; // height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) short x_off; // x offset for the vir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) short y_off; // y offset for the vir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mdp_img_act;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) typedef struct RANGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned short min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned short max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) typedef struct POINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned short x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned short y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) POINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) typedef struct RECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned short xmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned short xmax; // width - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned short ymin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned short ymax; // height - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } RECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) typedef struct RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned char r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned char g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned char b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned char res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) typedef struct MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned char mmu_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) uint32_t mmu_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } MMU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) typedef struct COLOR_FILL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) short gr_x_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) short gr_y_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) short gr_x_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) short gr_y_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) short gr_x_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) short gr_y_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) short gr_x_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) short gr_y_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) //u8 cp_gr_saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) COLOR_FILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) typedef struct FADING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uint8_t b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) uint8_t g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uint8_t r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint8_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FADING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) typedef struct line_draw_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) POINT start_point; /* LineDraw_start_point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) POINT end_point; /* LineDraw_end_point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint32_t color; /* LineDraw_color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint32_t flag; /* (enum) LineDrawing mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uint32_t line_width; /* range 1~16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) line_draw_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct rga_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint8_t render_mode; /* (enum) process mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rga_img_info_t src; /* src image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rga_img_info_t dst; /* dst image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rga_img_info_t pat; /* patten image info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long rop_mask_addr; /* rop4 mask addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long LUT_addr; /* LUT addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) RECT clip; /* dst clip window default value is dst_vir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* value from [0, w-1] / [0, h-1]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int32_t sina; /* dst angle default value 0 16.16 scan from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int32_t cosa; /* dst angle default value 0 16.16 scan from table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uint16_t alpha_rop_flag; /* alpha rop process flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* ([0] = 1 alpha_rop_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* ([1] = 1 rop enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* ([2] = 1 fading_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* ([3] = 1 PD_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* ([4] = 1 alpha cal_mode_sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* ([5] = 1 dither_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* ([6] = 1 gradient fill mode sel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* ([7] = 1 AA_enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) uint32_t color_key_max; /* color key max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uint32_t color_key_min; /* color key min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint32_t fg_color; /* foreground color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) uint32_t bg_color; /* background color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) COLOR_FILL gr_color; /* color fill use gradient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) line_draw_t line_draw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FADING fading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint8_t PD_mode; /* porter duff alpha mode sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint8_t alpha_global_value; /* global alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint8_t endian_mode; /* 0/big endian 1/little endian*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint8_t rotate_mode; /* (enum) rotate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* 0x0, no rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* 0x1, rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* 0x2, x_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* 0x3, y_mirror */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MMU mmu_info; /* mmu information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* ([2~3] rop mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* ([4] zero mode en) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* ([5] dst alpha mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint8_t src_trans_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct sg_table *sg_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct sg_table *sg_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct dma_buf_attachment *attach_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct dma_buf_attachment *attach_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) typedef struct TILE_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int64_t matrix[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uint16_t tile_y_num; /* y axis tile num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint16_t tile_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint16_t tile_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int16_t tile_start_x_coor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int16_t tile_start_y_coor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int32_t tile_xoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int32_t tile_yoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int32_t tile_temp_xstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int32_t tile_temp_ystart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* src tile incr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int32_t x_dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int32_t x_dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int32_t y_dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int32_t y_dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mdp_img_act dst_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) TILE_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct rga_mmu_buf_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int32_t front;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int32_t back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int32_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int32_t curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned int *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int *buf_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * struct for process session which connect to rga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @author ZhangShengqin (2012-2-15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) typedef struct rga_session {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* a linked list of data so we can access them for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct list_head list_session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* a linked list of register data waiting for process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct list_head waiting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* a linked list of register data in processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct list_head running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* all coommand this thread done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) atomic_t done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pid_t pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) atomic_t task_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) atomic_t num_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } rga_session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct rga_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rga_session *session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct list_head session_link; /* link to rga service session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct list_head status_link; /* link to register set list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) uint32_t sys_reg[RGA_REG_CTRL_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) uint32_t cmd_reg[RGA_REG_CMD_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) uint32_t *MMU_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) uint32_t MMU_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) //atomic_t int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) //struct rga_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct sg_table *sg_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct sg_table *sg_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct dma_buf_attachment *attach_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct dma_buf_attachment *attach_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) typedef struct rga_service_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct timer_list timer; /* timer for power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct list_head waiting; /* link to link_reg in struct vpu_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct list_head running; /* link to link_reg in struct vpu_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct list_head done; /* link to link_reg in struct vpu_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct list_head session; /* link to list_session in struct vpu_session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) atomic_t total_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct rga_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint32_t cmd_buff[28*8];/* cmd_buff for rga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint32_t *pre_scale_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned long *pre_scale_buf_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) atomic_t int_disable; /* 0 int enable 1 int disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) atomic_t cmd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) atomic_t src_format_swt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int last_prc_src_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) atomic_t rga_working;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 dev_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) //struct rga_req req[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct mutex mutex; // mutex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } rga_service_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define RGA_BASE 0x1010c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #elif defined(CONFIG_ARCH_RK30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define RGA_BASE 0x10114000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) //General Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define RGA_SYS_CTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define RGA_CMD_CTRL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define RGA_CMD_ADDR 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define RGA_STATUS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define RGA_INT 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define RGA_AXI_ID 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define RGA_MMU_STA_CTRL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define RGA_MMU_STA 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define RGA_VERSION 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) //Command code start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define RGA_MODE_CTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) //Source Image Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define RGA_SRC_Y_MST 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define RGA_SRC_CB_MST 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define RGA_MASK_READ_MST 0x108 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define RGA_SRC_CR_MST 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define RGA_SRC_VIR_INFO 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define RGA_SRC_ACT_INFO 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define RGA_SRC_X_PARA 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define RGA_SRC_Y_PARA 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define RGA_SRC_TILE_XINFO 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define RGA_SRC_TILE_YINFO 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define RGA_SRC_TILE_H_INCR 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define RGA_SRC_TILE_V_INCR 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define RGA_SRC_TILE_OFFSETX 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define RGA_SRC_TILE_OFFSETY 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define RGA_SRC_BG_COLOR 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define RGA_SRC_FG_COLOR 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define RGA_LINE_DRAWING_COLOR 0x13c //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define RGA_SRC_TR_COLOR0 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define RGA_CP_GR_A 0x140 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define RGA_SRC_TR_COLOR1 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define RGA_CP_GR_B 0x144 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define RGA_LINE_DRAW 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define RGA_PAT_START_POINT 0x148 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) //Destination Image Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define RGA_DST_MST 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define RGA_LUT_MST 0x14c //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define RGA_PAT_MST 0x14c //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define RGA_LINE_DRAWING_MST 0x14c //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define RGA_DST_VIR_INFO 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RGA_DST_CTR_INFO 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define RGA_LINE_DRAW_XY_INFO 0x154 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) //Alpha/ROP Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define RGA_ALPHA_CON 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RGA_PAT_CON 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define RGA_ROP_CON0 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define RGA_CP_GR_G 0x160 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define RGA_PRESCL_CB_MST 0x160 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define RGA_ROP_CON1 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define RGA_CP_GR_R 0x164 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define RGA_PRESCL_CR_MST 0x164 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) //MMU Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define RGA_FADING_CON 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define RGA_MMU_CTRL 0x168 //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define RGA_MMU_TBL 0x16c //repeat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define RGA_YUV_OUT_CFG 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define RGA_DST_UV_MST 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define RGA_BLIT_COMPLETE_EVENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) long rga_ioctl_kernel(struct rga_req *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif /*_RK29_IPP_DRIVER_H_*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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