Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  GOVR registers list for WM8505 chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *   Based on VIA/WonderMedia wm8510-govrh-reg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *   http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *         drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _WM8505FB_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _WM8505FB_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Color space select register, default value 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *   BIT0 GOVRH_DVO_YUV2RGB_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *   BIT1 GOVRH_VGA_YUV2RGB_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *   BIT2 GOVRH_RGB_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *   BIT3 GOVRH_DAC_CLKINV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *   BIT4 GOVRH_BLANK_ZERO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WMT_GOVR_COLORSPACE	0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Another colorspace select register, default value 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *   BIT0 GOVRH_DVO_RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *   BIT1 GOVRH_DVO_YUV422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WMT_GOVR_COLORSPACE1	 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WMT_GOVR_CONTRAST	0x1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WMT_GOVR_BRGHTNESS	0x1bc /* incompatible with RGB? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Framubeffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WMT_GOVR_FBADDR		 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WMT_GOVR_FBADDR1	 0x94 /* UV offset in YUV mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Offset of visible window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WMT_GOVR_XPAN		 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WMT_GOVR_YPAN		 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WMT_GOVR_XRES		 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WMT_GOVR_XRES_VIRTUAL	 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WMT_GOVR_MIF_ENABLE	 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WMT_GOVR_FHI		 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WMT_GOVR_REG_UPDATE	 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  *   BIT0 GOVRH_DVO_OUTWIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  *   BIT1 GOVRH_DVO_SYNC_POLAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  *   BIT2 GOVRH_DVO_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WMT_GOVR_DVO_SET	0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Timing generator? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WMT_GOVR_TG		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WMT_GOVR_TIMING_H_ALL	0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WMT_GOVR_TIMING_V_ALL	0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WMT_GOVR_TIMING_V_START	0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WMT_GOVR_TIMING_V_END	0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WMT_GOVR_TIMING_H_START	0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WMT_GOVR_TIMING_H_END	0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WMT_GOVR_TIMING_V_SYNC	0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WMT_GOVR_TIMING_H_SYNC	0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* _WM8505FB_REGS_H */