^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/video/w100fb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Frame Buffer Device for ATI w100 (Wallaby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2002, ATI Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004-2005 Richard Purdie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2005 Ian Molton <spyro@f2s.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * w32xx support by Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #if !defined (_W100FB_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _W100FB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Block CIF Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define mmCHIP_ID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define mmREVISION_ID 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define mmWRAP_BUF_A 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define mmWRAP_BUF_B 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define mmWRAP_TOP_DIR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define mmWRAP_START_DIR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define mmCIF_CNTL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define mmCFGREG_BASE 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define mmCIF_IO 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define mmCIF_READ_DBG 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define mmCIF_WRITE_DBG 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define cfgIND_ADDR_A_0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define cfgIND_ADDR_A_1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define cfgIND_ADDR_A_2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define cfgIND_DATA_A 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define cfgREG_BASE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define cfgINTF_CNTL 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define cfgSTATUS 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define cfgCPU_DEFAULTS 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define cfgIND_ADDR_B_0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define cfgIND_ADDR_B_1 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define cfgIND_ADDR_B_2 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define cfgIND_DATA_B 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define cfgPM4_RPTR 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define cfgSCRATCH 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define cfgPM4_WRPTR_0 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define cfgPM4_WRPTR_1 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Block CIF End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Block CP Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define mmSCRATCH_UMSK 0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define mmSCRATCH_ADDR 0x0284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define mmGEN_INT_CNTL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define mmGEN_INT_STATUS 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Block CP End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Block DISPLAY Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define mmLCD_FORMAT 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define mmGRAPHIC_CTRL 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define mmGRAPHIC_OFFSET 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define mmGRAPHIC_PITCH 0x041C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define mmCRTC_TOTAL 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define mmACTIVE_H_DISP 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define mmACTIVE_V_DISP 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define mmGRAPHIC_H_DISP 0x042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define mmGRAPHIC_V_DISP 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define mmVIDEO_CTRL 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define mmGRAPHIC_KEY 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define mmBRIGHTNESS_CNTL 0x045C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define mmDISP_INT_CNTL 0x0488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define mmCRTC_SS 0x048C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define mmCRTC_LS 0x0490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define mmCRTC_REV 0x0494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define mmCRTC_DCLK 0x049C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define mmCRTC_GS 0x04A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define mmCRTC_VPOS_GS 0x04A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define mmCRTC_GCLK 0x04A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define mmCRTC_GOE 0x04AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define mmCRTC_FRAME 0x04B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define mmCRTC_FRAME_VPOS 0x04B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define mmGPIO_DATA 0x04B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define mmGPIO_CNTL1 0x04BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define mmGPIO_CNTL2 0x04C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define mmLCDD_CNTL1 0x04C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define mmLCDD_CNTL2 0x04C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define mmGENLCD_CNTL1 0x04CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define mmGENLCD_CNTL2 0x04D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define mmDISP_DEBUG 0x04D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define mmDISP_DB_BUF_CNTL 0x04D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define mmDISP_CRC_SIG 0x04DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define mmCRTC_DEFAULT_COUNT 0x04E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define mmLCD_BACKGROUND_COLOR 0x04E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define mmCRTC_PS2 0x04E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define mmCRTC_PS2_VPOS 0x04EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define mmCRTC_PS1_ACTIVE 0x04F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define mmCRTC_PS1_NACTIVE 0x04F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define mmCRTC_GCLK_EXT 0x04F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define mmCRTC_ALW 0x04FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define mmCRTC_ALW_VPOS 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define mmCRTC_PSK 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define mmCRTC_PSK_HPOS 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define mmCRTC_CV4_START 0x050C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define mmCRTC_CV4_END 0x0510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define mmCRTC_CV4_HPOS 0x0514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define mmCRTC_ECK 0x051C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define mmREFRESH_CNTL 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define mmGENLCD_CNTL3 0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define mmGPIO_DATA2 0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define mmGPIO_CNTL3 0x052C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define mmGPIO_CNTL4 0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define mmCHIP_STRAP 0x0534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define mmDISP_DEBUG2 0x0538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define mmDEBUG_BUS_CNTL 0x053C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define mmGAMMA_VALUE1 0x0540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define mmGAMMA_VALUE2 0x0544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define mmGAMMA_SLOPE 0x0548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define mmGEN_STATUS 0x054C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define mmHW_INT 0x0550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Block DISPLAY End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Block GFX Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define mmDST_OFFSET 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define mmDST_PITCH 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define mmDST_Y_X 0x1038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define mmDST_WIDTH_HEIGHT 0x1198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define mmDP_GUI_MASTER_CNTL 0x106C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define mmBRUSH_OFFSET 0x108C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define mmBRUSH_Y_X 0x1074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define mmDP_BRUSH_FRGD_CLR 0x107C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define mmSRC_OFFSET 0x11AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define mmSRC_PITCH 0x11B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define mmSRC_Y_X 0x1034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define mmDEFAULT_PITCH_OFFSET 0x10A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define mmSC_TOP_LEFT 0x11BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define mmSC_BOTTOM_RIGHT 0x11C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define mmSRC_SC_BOTTOM_RIGHT 0x11C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define mmGLOBAL_ALPHA 0x1210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define mmFILTER_COEF 0x1214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define mmMVC_CNTL_START 0x11E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define mmE2_ARITHMETIC_CNTL 0x1220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define mmDP_CNTL 0x11C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define mmDP_CNTL_DST_DIR 0x11CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define mmDP_DATATYPE 0x12C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define mmDP_MIX 0x12C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define mmDP_WRITE_MSK 0x12CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define mmENG_CNTL 0x13E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define mmENG_PERF_CNT 0x13F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Block GFX End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Block IDCT Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define mmIDCT_RUNS 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define mmIDCT_LEVELS 0x0C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define mmIDCT_CONTROL 0x0C3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define mmIDCT_AUTH_CONTROL 0x0C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define mmIDCT_AUTH 0x0C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Block IDCT End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Block MC Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define mmMEM_CNTL 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define mmMEM_ARB 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define mmMC_FB_LOCATION 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define mmMEM_EXT_CNTL 0x018C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define mmMC_EXT_MEM_LOCATION 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define mmMEM_EXT_TIMING_CNTL 0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define mmMEM_SDRAM_MODE_REG 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define mmMEM_IO_CNTL 0x019C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define mmMC_DEBUG 0x01A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define mmMC_BIST_CTRL 0x01A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define mmMC_BIST_COLLAR_READ 0x01A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define mmTC_MISMATCH 0x01AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define mmMC_PERF_MON_CNTL 0x01B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define mmMC_PERF_COUNTERS 0x01B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Block MC End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Block BM Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define mmBM_EXT_MEM_BANDWIDTH 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define mmBM_OFFSET 0x0A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define mmBM_MEM_EXT_TIMING_CNTL 0x0A08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define mmBM_MEM_EXT_CNTL 0x0A0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define mmBM_MEM_MODE_REG 0x0A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define mmBM_MEM_IO_CNTL 0x0A18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define mmBM_CONFIG 0x0A1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define mmBM_STATUS 0x0A20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define mmBM_DEBUG 0x0A24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define mmBM_PERF_MON_CNTL 0x0A28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define mmBM_PERF_COUNTERS 0x0A2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define mmBM_PERF2_MON_CNTL 0x0A30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define mmBM_PERF2_COUNTERS 0x0A34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Block BM End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Block RBBM Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define mmWAIT_UNTIL 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define mmISYNC_CNTL 0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define mmRBBM_STATUS 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define mmRBBM_CNTL 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define mmNQWAIT_UNTIL 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Block RBBM End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Block CG Start: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define mmCLK_PIN_CNTL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define mmPLL_REF_FB_DIV 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define mmPLL_CNTL 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define mmSCLK_CNTL 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define mmPCLK_CNTL 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define mmCLK_TEST_CNTL 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define mmPWRMGT_CNTL 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define mmPWRMGT_STATUS 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Block CG End: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* default value definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define defWRAP_TOP_DIR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define defWRAP_START_DIR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define defCFGREG_BASE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define defCIF_IO 0x000C0902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define defINTF_CNTL 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define defCPU_DEFAULTS 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define defHW_INT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define defMC_EXT_MEM_LOCATION 0x07ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define defTC_MISMATCH 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define W100_CFG_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define W100_CFG_LEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define W100_REG_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define W100_REG_LEN 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MEM_INT_BASE_VALUE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MEM_EXT_BASE_VALUE 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MEM_INT_SIZE 0x05ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MEM_WINDOW_BASE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MEM_WINDOW_SIZE 0xf00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define WRAP_BUF_BASE_VALUE 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define WRAP_BUF_TOP_VALUE 0xbffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CHIP_ID_W100 0x57411002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CHIP_ID_W3200 0x56441002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CHIP_ID_W3220 0x57441002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Register structure definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct wrap_top_dir_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 top_addr : 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 : 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) union wrap_top_dir_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct wrap_top_dir_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct wrap_start_dir_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 start_addr : 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 : 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) union wrap_start_dir_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct wrap_start_dir_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct cif_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 swap_reg : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 swap_fbuf_1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 swap_fbuf_2 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 swap_fbuf_3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 pmi_int_disable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 pmi_schmen_disable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 intb_oe : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 en_wait_to_compensate_dq_prop_dly : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 compensate_wait_rd_size : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 wait_asserted_timeout_val : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 wait_masked_val : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 en_wait_timeout : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 en_one_clk_setup_before_wait : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 interrupt_active_high : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 en_overwrite_straps : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 strap_wait_active_hi : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 lat_busy_count : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 lat_rd_pm4_sclk_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 dis_system_bits : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 dis_mr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 cif_spare_1 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) union cif_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct cif_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct cfgreg_base_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 cfgreg_base : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) union cfgreg_base_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct cfgreg_base_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct cif_io_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 dq_srp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 dq_srn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 dq_sp : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 dq_sn : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 waitb_srp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 waitb_srn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 waitb_sp : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 waitb_sn : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 intb_srp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 intb_srn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 intb_sp : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 intb_sn : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) union cif_io_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct cif_io_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct cif_read_dbg_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 unpacker_pre_fetch_trig_gen : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 dly_second_rd_fetch_trig : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 rst_rd_burst_id : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 dis_rd_burst_id : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 en_block_rd_when_packer_is_not_emp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 dis_pre_fetch_cntl_sm : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 rbbm_chrncy_dis : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 rbbm_rd_after_wr_lat : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 dis_be_during_rd : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 one_clk_invalidate_pulse : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 dis_chnl_priority : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 rst_read_path_a_pls : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 rst_read_path_b_pls : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 dis_reg_rd_fetch_trig : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 dis_rd_fetch_trig_from_ind_addr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 dis_rd_same_byte_to_trig_fetch : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 dis_dir_wrap : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 dis_ring_buf_to_force_dec : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 dis_addr_comp_in_16bit : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 clr_w : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 err_rd_tag_is_3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 err_load_when_ful_a : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 err_load_when_ful_b : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) union cif_read_dbg_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct cif_read_dbg_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct cif_write_dbg_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 packer_timeout_count : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 en_upper_load_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 en_chnl_change_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 dis_addr_comp_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 dis_load_same_byte_addr_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 dis_timeout_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 dis_timeout_during_rbbm : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 dis_packer_ful_during_rbbm_timeout : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 en_dword_split_to_rbbm : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 en_dummy_val : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 dummy_val_sel : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 mask_pm4_wrptr_dec : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 dis_mc_clean_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 err_two_reqi_during_ful : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 err_reqi_during_idle_clk : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 err_global : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 en_wr_buf_dbg_load : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 en_wr_buf_dbg_path : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 sel_wr_buf_byte : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 dis_rd_flush_wr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 dis_packer_ful_cond : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 dis_invalidate_by_ops_chnl : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 en_halt_when_reqi_err : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 cif_spare_2 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) union cif_write_dbg_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct cif_write_dbg_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct intf_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned char ad_inc_a : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned char ring_buf_a : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned char rd_fetch_trigger_a : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned char rd_data_rdy_a : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned char ad_inc_b : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned char ring_buf_b : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned char rd_fetch_trigger_b : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned char rd_data_rdy_b : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) union intf_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned char val : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct intf_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct cpu_defaults_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned char unpack_rd_data : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned char access_ind_addr_a : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned char access_ind_addr_b : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned char access_scratch_reg : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned char pack_wr_data : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned char transition_size : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned char en_read_buf_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned char rd_fetch_scratch : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) union cpu_defaults_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned char val : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct cpu_defaults_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct crtc_total_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 crtc_h_total : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 crtc_v_total : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) union crtc_total_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct crtc_total_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct crtc_ss_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 ss_start : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 ss_end : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 ss_align : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 ss_pol : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 ss_run_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 ss_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) union crtc_ss_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct crtc_ss_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct active_h_disp_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 active_h_start : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 active_h_end : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) union active_h_disp_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct active_h_disp_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct active_v_disp_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u32 active_v_start : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 active_v_end : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) union active_v_disp_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct active_v_disp_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct graphic_h_disp_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 graphic_h_start : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 graphic_h_end : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) union graphic_h_disp_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct graphic_h_disp_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct graphic_v_disp_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 graphic_v_start : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 graphic_v_end : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) union graphic_v_disp_u{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct graphic_v_disp_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct graphic_ctrl_t_w100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 color_depth : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 portrait_mode : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 low_power_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 req_freq : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u32 en_crtc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 en_graphic_req : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 en_graphic_crtc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 total_req_graphic : 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 lcd_pclk_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 lcd_sclk_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 pclk_running : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 sclk_running : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct graphic_ctrl_t_w32xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 color_depth : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 portrait_mode : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 low_power_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 req_freq : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 en_crtc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 en_graphic_req : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 en_graphic_crtc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 total_req_graphic : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 lcd_pclk_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 lcd_sclk_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 pclk_running : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 sclk_running : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) union graphic_ctrl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct graphic_ctrl_t_w100 f_w100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct graphic_ctrl_t_w32xx f_w32xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct video_ctrl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 video_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 keyer_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 en_video_req : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 en_graphic_req_video : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 en_video_crtc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 video_hor_exp : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 video_ver_exp : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 uv_combine : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 total_req_video : 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 video_ch_sel : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 video_portrait : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 yuv2rgb_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 yuv2rgb_option : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 video_inv_hor : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 video_inv_ver : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 gamma_sel : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 dis_limit : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 en_uv_hblend : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 rgb_gamma_sel : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) union video_ctrl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct video_ctrl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct disp_db_buf_cntl_rd_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 en_db_buf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 update_db_buf_done : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 db_buf_cntl : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) union disp_db_buf_cntl_rd_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct disp_db_buf_cntl_rd_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct disp_db_buf_cntl_wr_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 en_db_buf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 update_db_buf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 db_buf_cntl : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) union disp_db_buf_cntl_wr_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct disp_db_buf_cntl_wr_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct gamma_value1_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 gamma1 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 gamma2 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 gamma3 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 gamma4 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) union gamma_value1_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct gamma_value1_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct gamma_value2_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 gamma5 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 gamma6 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 gamma7 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 gamma8 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) union gamma_value2_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct gamma_value2_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct gamma_slope_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 slope1 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 slope2 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 slope3 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u32 slope4 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 slope5 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 slope6 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 slope7 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 slope8 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) union gamma_slope_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct gamma_slope_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct mc_ext_mem_location_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 mc_ext_mem_start : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 mc_ext_mem_top : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) union mc_ext_mem_location_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct mc_ext_mem_location_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct mc_fb_location_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 mc_fb_start : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 mc_fb_top : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) union mc_fb_location_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct mc_fb_location_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct clk_pin_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 osc_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 osc_gain : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 dont_use_xtalin : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 xtalin_pm_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 xtalin_dbl_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 cg_debug : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) union clk_pin_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct clk_pin_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct pll_ref_fb_div_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 pll_ref_div : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 pll_fb_div_int : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 pll_fb_div_frac : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 pll_reset_time : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 pll_lock_time : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) union pll_ref_fb_div_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct pll_ref_fb_div_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct pll_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 pll_pwdn : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 pll_reset : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 pll_pm_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 pll_mode : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 pll_refclk_sel : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 pll_fbclk_sel : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 pll_tcpoff : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 pll_pcp : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 pll_pvg : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 pll_vcofr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 pll_ioffset : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 pll_pecc_mode : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 pll_pecc_scon : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 pll_dactal : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 pll_cp_clip : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 pll_conf : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 pll_mbctrl : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 pll_ring_off : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) union pll_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct pll_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct sclk_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 sclk_src_sel : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 sclk_post_div_fast : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 sclk_clkon_hys : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 sclk_post_div_slow : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 disp_cg_ok2switch_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 sclk_force_reg : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 sclk_force_disp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 sclk_force_mc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 sclk_force_extmc : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 sclk_force_cp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 sclk_force_e2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 sclk_force_e3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 sclk_force_idct : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 sclk_force_bist : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 busy_extend_cp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 busy_extend_e2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 busy_extend_e3 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 busy_extend_idct : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) union sclk_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct sclk_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct pclk_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 pclk_src_sel : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 pclk_post_div : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 pclk_force_disp : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) union pclk_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct pclk_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define TESTCLK_SRC_PLL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define TESTCLK_SRC_SCLK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define TESTCLK_SRC_PCLK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* 4 and 5 seem to by XTAL/M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define TESTCLK_SRC_XTAL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct clk_test_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 testclk_sel : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 start_check_freq : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 tstcount_rst : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 test_count : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) union clk_test_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct clk_test_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct pwrmgt_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u32 pwm_enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u32 pwm_mode_req : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 pwm_wakeup_cond : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u32 pwm_fast_noml_hw_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 pwm_noml_fast_hw_en : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 pwm_fast_noml_cond : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 pwm_noml_fast_cond : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 pwm_idle_timer : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 pwm_busy_timer : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) union pwrmgt_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct pwrmgt_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define SRC_DATATYPE_EQU_DST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define ROP3_SRCCOPY 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define ROP3_PATCOPY 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define GMC_BRUSH_SOLID_COLOR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define GMC_BRUSH_NONE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define DP_SRC_MEM_RECTANGULAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define DP_OP_ROP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct dp_gui_master_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 gmc_src_pitch_offset_cntl : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 gmc_dst_pitch_offset_cntl : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 gmc_src_clipping : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 gmc_dst_clipping : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 gmc_brush_datatype : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 gmc_dst_datatype : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 gmc_src_datatype : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 gmc_byte_pix_order : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 gmc_default_sel : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 gmc_rop3 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 gmc_dp_src_source : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 gmc_clr_cmp_fcn_dis : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 gmc_wr_msk_dis : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 gmc_dp_op : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) union dp_gui_master_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct dp_gui_master_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct rbbm_status_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 cmdfifo_avail : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 hirq_on_rbb : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 cprq_on_rbb : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u32 cfrq_on_rbb : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 hirq_in_rtbuf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 cprq_in_rtbuf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 cfrq_in_rtbuf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 cf_pipe_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 eng_ev_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 cp_cmdstrm_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 e2_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 rb2d_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 rb3d_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 se_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 re_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u32 tam_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u32 tdm_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u32 pb_busy : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 gui_active : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) union rbbm_status_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct rbbm_status_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct dp_datatype_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u32 dp_dst_datatype : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 dp_brush_datatype : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 dp_src2_type : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 dp_src2_datatype : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 dp_src_datatype : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u32 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 dp_byte_pix_order : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) union dp_datatype_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct dp_datatype_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct dp_mix_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 dp_src_source : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 dp_src2_source : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 dp_rop3 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 dp_op : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) union dp_mix_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct dp_mix_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct eng_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 erc_reg_rd_ws : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 erc_reg_wr_ws : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 erc_idle_reg_wr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 dis_engine_triggers : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u32 dis_rop_src_uses_dst_w_h : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 dis_src_uses_dst_dirmaj : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 : 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 force_3dclk_when_2dclk : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 : 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) union eng_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct eng_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct dp_cntl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 dst_x_dir : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 dst_y_dir : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u32 src_x_dir : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 src_y_dir : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 dst_major_x : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 src_major_x : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u32 : 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) union dp_cntl_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct dp_cntl_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct dp_cntl_dst_dir_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u32 : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 dst_y_dir : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u32 : 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 dst_x_dir : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) union dp_cntl_dst_dir_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u32 val : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct dp_cntl_dst_dir_t f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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