^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/video/w100fb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Frame Buffer Device for ATI Imageon w100 (Wallaby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2002, ATI Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004-2006 Richard Purdie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2005 Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2006 Alberto Mardegan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Rewritten for 2.6 by Richard Purdie <rpurdie@rpsys.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Generic platform support by Ian Molton <spyro@f2s.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * and Richard Purdie <rpurdie@rpsys.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * w32xx support by Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Hardware acceleration support by Alberto Mardegan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * <mardy@users.sourceforge.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <video/w100fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "w100fb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void w100_suspend(u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void w100_vsync(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void w100_hw_init(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void w100_pwm_setup(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void w100_init_clocks(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void w100_setup_memory(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void w100_init_lcd(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void w100_set_dispregs(struct w100fb_par*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void w100_update_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void w100_update_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void calc_hsync(struct w100fb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void w100_init_graphic_engine(struct w100fb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct w100_pll_info *w100_get_xtal_table(unsigned int freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Pseudo palette size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAX_PALETTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define W100_SUSPEND_EXTMEM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define W100_SUSPEND_ALL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BITS_PER_PIXEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Remapped addresses for base cfg, memmapped regs and the frame buffer itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void __iomem *remapped_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void __iomem *remapped_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void __iomem *remapped_fbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REMAPPED_FB_LEN 0x15ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* This is the offset in the w100's address space we map the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) framebuffer memory to. We use the position of external memory as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) we can remap internal memory to there if external isn't present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define W100_FB_BASE MEM_EXT_BASE_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Sysfs functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static ssize_t flip_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return sprintf(buf, "%d\n",par->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static ssize_t flip_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) flip = simple_strtoul(buf, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (flip > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) par->flip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) par->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) w100_update_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) w100_set_dispregs(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) w100_update_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) calc_hsync(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static DEVICE_ATTR_RW(flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static ssize_t w100fb_reg_read(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long regs, param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regs = simple_strtoul(buf, NULL, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) param = readl(remapped_regs + regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) printk("Read Register 0x%08lX: 0x%08lX\n", regs, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static DEVICE_ATTR(reg_read, 0200, NULL, w100fb_reg_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static ssize_t w100fb_reg_write(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long regs, param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) sscanf(buf, "%lx %lx", ®s, ¶m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (regs <= 0x2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) printk("Write Register 0x%08lX: 0x%08lX\n", regs, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(param, remapped_regs + regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static DEVICE_ATTR(reg_write, 0200, NULL, w100fb_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static ssize_t fastpllclk_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return sprintf(buf, "%d\n",par->fastpll_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static ssize_t fastpllclk_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (simple_strtoul(buf, NULL, 10) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) par->fastpll_mode=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) printk("w100fb: Using fast system clock (if possible)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) par->fastpll_mode=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) printk("w100fb: Using normal system clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) w100_init_clocks(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) calc_hsync(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static DEVICE_ATTR_RW(fastpllclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct attribute *w100fb_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) &dev_attr_fastpllclk.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) &dev_attr_reg_read.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) &dev_attr_reg_write.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &dev_attr_flip.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ATTRIBUTE_GROUPS(w100fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Some touchscreens need hsync information from the video driver to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * function correctly. We export it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long w100fb_get_hsynclen(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* If display is blanked/suspended, hsync isn't active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (par->blanked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return par->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EXPORT_SYMBOL(w100fb_get_hsynclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void w100fb_clear_screen(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) memset_io(remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), 0, (par->xres * par->yres * BITS_PER_PIXEL/8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Set a palette value from rgb components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int w100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u_int trans, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * If greyscale is true, then we convert the RGB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * to greyscale no matter what visual we are using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (info->var.grayscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) red = green = blue = (19595 * red + 38470 * green + 7471 * blue) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 16-bit True Colour. We encode the RGB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * according to the RGB bitfield information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (regno < MAX_PALETTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 *pal = info->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val = (red & 0xf800) | ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pal[regno] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Blank the display based on value in blank_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int w100fb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct w100fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct w100_tg_info *tg = par->mach->tg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch(blank_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case FB_BLANK_NORMAL: /* Normal blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case FB_BLANK_POWERDOWN: /* Poweroff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (par->blanked == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if(tg && tg->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tg->suspend(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) par->blanked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case FB_BLANK_UNBLANK: /* Unblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (par->blanked != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if(tg && tg->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tg->resume(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) par->blanked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void w100_fifo_wait(int entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) union rbbm_status_u status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for (i = 0; i < 2000000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) status.val = readl(remapped_regs + mmRBBM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (status.f.cmdfifo_avail >= entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) printk(KERN_ERR "w100fb: FIFO Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int w100fb_sync(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) union rbbm_status_u status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < 2000000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) status.val = readl(remapped_regs + mmRBBM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!status.f.gui_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) printk(KERN_ERR "w100fb: Graphic engine timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void w100_init_graphic_engine(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) union dp_gui_master_cntl_u gmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) union dp_mix_u dp_mix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) union dp_datatype_u dp_datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) union dp_cntl_u dp_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) w100_fifo_wait(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(par->xres, remapped_regs + mmDST_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(par->xres, remapped_regs + mmSRC_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) w100_fifo_wait(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writel(0, remapped_regs + mmSC_TOP_LEFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) w100_fifo_wait(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dp_cntl.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dp_cntl.f.dst_x_dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dp_cntl.f.dst_y_dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dp_cntl.f.src_x_dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dp_cntl.f.src_y_dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dp_cntl.f.dst_major_x = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dp_cntl.f.src_major_x = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writel(dp_cntl.val, remapped_regs + mmDP_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) gmc.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) gmc.f.gmc_src_pitch_offset_cntl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) gmc.f.gmc_dst_pitch_offset_cntl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) gmc.f.gmc_src_clipping = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) gmc.f.gmc_dst_clipping = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) gmc.f.gmc_dst_datatype = 3; /* from DstType_16Bpp_444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) gmc.f.gmc_src_datatype = SRC_DATATYPE_EQU_DST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) gmc.f.gmc_byte_pix_order = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) gmc.f.gmc_default_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) gmc.f.gmc_rop3 = ROP3_SRCCOPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) gmc.f.gmc_clr_cmp_fcn_dis = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) gmc.f.gmc_wr_msk_dis = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) gmc.f.gmc_dp_op = DP_OP_ROP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dp_datatype.val = dp_mix.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dp_datatype.f.dp_dst_datatype = gmc.f.gmc_dst_datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dp_datatype.f.dp_brush_datatype = gmc.f.gmc_brush_datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dp_datatype.f.dp_src2_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dp_datatype.f.dp_src2_datatype = gmc.f.gmc_src_datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dp_datatype.f.dp_src_datatype = gmc.f.gmc_src_datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dp_datatype.f.dp_byte_pix_order = gmc.f.gmc_byte_pix_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dp_mix.f.dp_src_source = gmc.f.gmc_dp_src_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dp_mix.f.dp_src2_source = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dp_mix.f.dp_rop3 = gmc.f.gmc_rop3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dp_mix.f.dp_op = gmc.f.gmc_dp_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) writel(dp_mix.val, remapped_regs + mmDP_MIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void w100fb_fillrect(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) const struct fb_fillrect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) union dp_gui_master_cntl_u gmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (info->state != FBINFO_STATE_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (info->flags & FBINFO_HWACCEL_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cfb_fillrect(info, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) gmc.f.gmc_rop3 = ROP3_PATCOPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) gmc.f.gmc_brush_datatype = GMC_BRUSH_SOLID_COLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) w100_fifo_wait(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(rect->color, remapped_regs + mmDP_BRUSH_FRGD_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) w100_fifo_wait(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel((rect->dy << 16) | (rect->dx & 0xffff), remapped_regs + mmDST_Y_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel((rect->width << 16) | (rect->height & 0xffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) remapped_regs + mmDST_WIDTH_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void w100fb_copyarea(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const struct fb_copyarea *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 h = area->height, w = area->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) union dp_gui_master_cntl_u gmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (info->state != FBINFO_STATE_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (info->flags & FBINFO_HWACCEL_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cfb_copyarea(info, area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) gmc.f.gmc_rop3 = ROP3_SRCCOPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) w100_fifo_wait(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) w100_fifo_wait(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel((sy << 16) | (sx & 0xffff), remapped_regs + mmSRC_Y_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writel((dy << 16) | (dx & 0xffff), remapped_regs + mmDST_Y_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writel((w << 16) | (h & 0xffff), remapped_regs + mmDST_WIDTH_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Change the resolution by calling the appropriate hardware functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void w100fb_activate_var(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct w100_tg_info *tg = par->mach->tg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) w100_pwm_setup(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) w100_setup_memory(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) w100_init_clocks(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) w100fb_clear_screen(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) w100_vsync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) w100_update_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) w100_init_lcd(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) w100_set_dispregs(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) w100_update_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) w100_init_graphic_engine(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) calc_hsync(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!par->blanked && tg && tg->change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tg->change(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Select the smallest mode that allows the desired resolution to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * displayed. If desired, the x and y parameters can be rounded up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * match the selected mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct w100_mode *w100fb_get_mode(struct w100fb_par *par, unsigned int *x, unsigned int *y, int saveval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct w100_mode *mode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct w100_mode *modelist = par->mach->modelist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0 ; i < par->mach->num_modes ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (modelist[i].xres >= *x && modelist[i].yres >= *y &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) modelist[i].xres < best_x && modelist[i].yres < best_y) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) best_x = modelist[i].xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) best_y = modelist[i].yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mode = &modelist[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if(modelist[i].xres >= *y && modelist[i].yres >= *x &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) modelist[i].xres < best_y && modelist[i].yres < best_x) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) best_x = modelist[i].yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) best_y = modelist[i].xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mode = &modelist[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (mode && saveval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *x = best_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) *y = best_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * w100fb_check_var():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Get the video params out of 'var'. If a value doesn't fit, round it up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * if it's too big, return -EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int w100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if(!w100fb_get_mode(par, &var->xres, &var->yres, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (par->mach->mem && ((var->xres*var->yres*BITS_PER_PIXEL/8) > (par->mach->mem->size+1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!par->mach->mem && ((var->xres*var->yres*BITS_PER_PIXEL/8) > (MEM_INT_SIZE+1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) var->xres_virtual = max(var->xres_virtual, var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) var->yres_virtual = max(var->yres_virtual, var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (var->bits_per_pixel > BITS_PER_PIXEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) var->bits_per_pixel = BITS_PER_PIXEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) var->red.offset = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) var->transp.offset = var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) var->nonstd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) var->height = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) var->width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) var->vmode = FB_VMODE_NONINTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) var->sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) var->pixclock = 0x04; /* 171521; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * w100fb_set_par():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Set the user defined part of the display for the specified console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * by looking at the values in info.var
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int w100fb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (par->xres != info->var.xres || par->yres != info->var.yres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) par->xres = info->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) par->yres = info->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) par->mode = w100fb_get_mode(par, &par->xres, &par->yres, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) info->fix.visual = FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) info->fix.ypanstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) info->fix.ywrapstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) info->fix.line_length = par->xres * BITS_PER_PIXEL / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mutex_lock(&info->mm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if ((par->xres*par->yres*BITS_PER_PIXEL/8) > (MEM_INT_SIZE+1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) par->extmem_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) info->fix.smem_len = par->mach->mem->size+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) par->extmem_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) info->fix.smem_len = MEM_INT_SIZE+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mutex_unlock(&info->mm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) w100fb_activate_var(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Frame buffer operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct fb_ops w100fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .fb_check_var = w100fb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .fb_set_par = w100fb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .fb_setcolreg = w100fb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .fb_blank = w100fb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .fb_fillrect = w100fb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .fb_copyarea = w100fb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .fb_sync = w100fb_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void w100fb_save_vidmem(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (par->extmem_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) memsize=par->mach->mem->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) par->saved_extmem = vmalloc(memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (par->saved_extmem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) memcpy_fromio(par->saved_extmem, remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) memsize=MEM_INT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) par->saved_intmem = vmalloc(memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (par->saved_intmem && par->extmem_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) memcpy_fromio(par->saved_intmem, remapped_fbuf + (W100_FB_BASE-MEM_INT_BASE_VALUE), memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else if (par->saved_intmem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) memcpy_fromio(par->saved_intmem, remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static void w100fb_restore_vidmem(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (par->extmem_active && par->saved_extmem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) memsize=par->mach->mem->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) memcpy_toio(remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), par->saved_extmem, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) vfree(par->saved_extmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) par->saved_extmem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (par->saved_intmem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) memsize=MEM_INT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (par->extmem_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) memcpy_toio(remapped_fbuf + (W100_FB_BASE-MEM_INT_BASE_VALUE), par->saved_intmem, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) memcpy_toio(remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), par->saved_intmem, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) vfree(par->saved_intmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) par->saved_intmem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int w100fb_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct fb_info *info = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct w100_tg_info *tg = par->mach->tg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) w100fb_save_vidmem(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if(tg && tg->suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tg->suspend(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) w100_suspend(W100_SUSPEND_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) par->blanked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int w100fb_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct fb_info *info = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct w100_tg_info *tg = par->mach->tg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) w100_hw_init(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) w100fb_activate_var(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) w100fb_restore_vidmem(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if(tg && tg->resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) tg->resume(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) par->blanked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define w100fb_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define w100fb_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int w100fb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct w100fb_mach_info *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct fb_info *info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct w100fb_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Remap the chip base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) remapped_base = ioremap(mem->start+W100_CFG_BASE, W100_CFG_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (remapped_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Map the register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) remapped_regs = ioremap(mem->start+W100_REG_BASE, W100_REG_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (remapped_regs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Identify the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) printk("Found ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) chip_id = readl(remapped_regs + mmCHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch(chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case CHIP_ID_W100: printk("w100"); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case CHIP_ID_W3200: printk("w3200"); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case CHIP_ID_W3220: printk("w3220"); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) printk("Unknown imageon chip ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) printk(" at 0x%08lx.\n", (unsigned long) mem->start+W100_CFG_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Remap the framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) remapped_fbuf = ioremap(mem->start+MEM_WINDOW_BASE, MEM_WINDOW_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (remapped_fbuf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) info=framebuffer_alloc(sizeof(struct w100fb_par), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) inf = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) par->chip_id = chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) par->mach = inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) par->fastpll_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) par->blanked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) par->pll_table=w100_get_xtal_table(inf->xtal_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!par->pll_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) printk(KERN_ERR "No matching Xtal definition found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) info->pseudo_palette = kmalloc_array(MAX_PALETTES, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!info->pseudo_palette) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) info->fbops = &w100fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) FBINFO_HWACCEL_FILLRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) info->node = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) info->screen_base = remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) info->screen_size = REMAPPED_FB_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) strcpy(info->fix.id, "w100fb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) info->fix.type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) info->fix.type_aux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) info->fix.accel = FB_ACCEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) info->fix.smem_start = mem->start+W100_FB_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) info->fix.mmio_start = mem->start+W100_REG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) info->fix.mmio_len = W100_REG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) par->mode = &inf->modelist[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if(inf->init_mode & INIT_MODE_ROTATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) info->var.xres = par->mode->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) info->var.yres = par->mode->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) info->var.xres = par->mode->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) info->var.yres = par->mode->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if(inf->init_mode &= INIT_MODE_FLIPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) par->flip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) par->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) info->var.xres_virtual = info->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) info->var.yres_virtual = info->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) info->var.pixclock = 0x04; /* 171521; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) info->var.sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) info->var.grayscale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) info->var.xoffset = info->var.yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) info->var.accel_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) info->var.activate = FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) w100_hw_init(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (w100fb_check_var(&info->var, info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (register_framebuffer(info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) fb_info(info, "%s frame buffer device\n", info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) kfree(info->pseudo_palette);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (remapped_fbuf != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) iounmap(remapped_fbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) remapped_fbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (remapped_regs != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) iounmap(remapped_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) remapped_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (remapped_base != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) iounmap(remapped_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) remapped_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int w100fb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct fb_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct w100fb_par *par=info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) vfree(par->saved_intmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) vfree(par->saved_extmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) kfree(info->pseudo_palette);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) iounmap(remapped_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) remapped_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) iounmap(remapped_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) remapped_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) iounmap(remapped_fbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) remapped_fbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* ------------------- chipset specific functions -------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static void w100_soft_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 val = readw((u16 __iomem *)remapped_base + cfgSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) writew(val | 0x08, (u16 __iomem *)remapped_base + cfgSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) writew(0x00, (u16 __iomem *)remapped_base + cfgSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static void w100_update_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) union disp_db_buf_cntl_wr_u disp_db_buf_wr_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Prevent display updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) disp_db_buf_wr_cntl.f.update_db_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) disp_db_buf_wr_cntl.f.en_db_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void w100_update_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) union disp_db_buf_cntl_wr_u disp_db_buf_wr_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Enable display updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) disp_db_buf_wr_cntl.f.update_db_buf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) disp_db_buf_wr_cntl.f.en_db_buf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) unsigned long w100fb_gpio_read(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (port==W100_GPIO_PORT_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) value = readl(remapped_regs + mmGPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) value = readl(remapped_regs + mmGPIO_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) void w100fb_gpio_write(int port, unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (port==W100_GPIO_PORT_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) writel(value, remapped_regs + mmGPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) writel(value, remapped_regs + mmGPIO_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) EXPORT_SYMBOL(w100fb_gpio_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) EXPORT_SYMBOL(w100fb_gpio_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Initialization of critical w100 hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void w100_hw_init(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 temp32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) union cif_cntl_u cif_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) union intf_cntl_u intf_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) union cfgreg_base_u cfgreg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) union wrap_top_dir_u wrap_top_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) union cif_read_dbg_u cif_read_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) union cpu_defaults_u cpu_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) union cif_write_dbg_u cif_write_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) union wrap_start_dir_u wrap_start_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) union cif_io_u cif_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct w100_gpio_regs *gpio = par->mach->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) w100_soft_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* This is what the fpga_init code does on reset. May be wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) but there is little info available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) writel(0x31, remapped_regs + mmSCRATCH_UMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) for (temp32 = 0; temp32 < 10000; temp32++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) readl(remapped_regs + mmSCRATCH_UMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) writel(0x30, remapped_regs + mmSCRATCH_UMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Set up CIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) cif_io.val = defCIF_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) writel((u32)(cif_io.val), remapped_regs + mmCIF_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) cif_write_dbg.val = readl(remapped_regs + mmCIF_WRITE_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cif_write_dbg.f.dis_packer_ful_during_rbbm_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) cif_write_dbg.f.en_dword_split_to_rbbm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) cif_write_dbg.f.dis_timeout_during_rbbm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) writel((u32) (cif_write_dbg.val), remapped_regs + mmCIF_WRITE_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) cif_read_dbg.val = readl(remapped_regs + mmCIF_READ_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) cif_read_dbg.f.dis_rd_same_byte_to_trig_fetch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) writel((u32) (cif_read_dbg.val), remapped_regs + mmCIF_READ_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cif_cntl.val = readl(remapped_regs + mmCIF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) cif_cntl.f.dis_system_bits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) cif_cntl.f.dis_mr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) cif_cntl.f.en_wait_to_compensate_dq_prop_dly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) cif_cntl.f.intb_oe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) cif_cntl.f.interrupt_active_high = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) writel((u32) (cif_cntl.val), remapped_regs + mmCIF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Setup cfgINTF_CNTL and cfgCPU defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) intf_cntl.val = defINTF_CNTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) intf_cntl.f.ad_inc_a = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) intf_cntl.f.ad_inc_b = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) intf_cntl.f.rd_data_rdy_a = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) intf_cntl.f.rd_data_rdy_b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) writeb((u8) (intf_cntl.val), remapped_base + cfgINTF_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cpu_default.val = defCPU_DEFAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) cpu_default.f.access_ind_addr_a = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) cpu_default.f.access_ind_addr_b = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) cpu_default.f.access_scratch_reg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) cpu_default.f.transition_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) writeb((u8) (cpu_default.val), remapped_base + cfgCPU_DEFAULTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* set up the apertures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) writeb((u8) (W100_REG_BASE >> 16), remapped_base + cfgREG_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) cfgreg_base.val = defCFGREG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) cfgreg_base.f.cfgreg_base = W100_CFG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) writel((u32) (cfgreg_base.val), remapped_regs + mmCFGREG_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) wrap_start_dir.val = defWRAP_START_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) wrap_start_dir.f.start_addr = WRAP_BUF_BASE_VALUE >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) writel((u32) (wrap_start_dir.val), remapped_regs + mmWRAP_START_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) wrap_top_dir.val = defWRAP_TOP_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) wrap_top_dir.f.top_addr = WRAP_BUF_TOP_VALUE >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) writel((u32) (wrap_top_dir.val), remapped_regs + mmWRAP_TOP_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) writel((u32) 0x2440, remapped_regs + mmRBBM_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Set the hardware to 565 colour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) temp32 = readl(remapped_regs + mmDISP_DEBUG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) temp32 &= 0xff7fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) temp32 |= 0x00800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) writel(temp32, remapped_regs + mmDISP_DEBUG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Initialise the GPIO lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) writel(gpio->init_data1, remapped_regs + mmGPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) writel(gpio->init_data2, remapped_regs + mmGPIO_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) writel(gpio->gpio_dir1, remapped_regs + mmGPIO_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) writel(gpio->gpio_oe1, remapped_regs + mmGPIO_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) writel(gpio->gpio_dir2, remapped_regs + mmGPIO_CNTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) writel(gpio->gpio_oe2, remapped_regs + mmGPIO_CNTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct power_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) union clk_pin_cntl_u clk_pin_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) union pll_ref_fb_div_u pll_ref_fb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) union pll_cntl_u pll_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) union sclk_cntl_u sclk_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) union pclk_cntl_u pclk_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) union pwrmgt_cntl_u pwrmgt_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int auto_mode; /* system clock auto changing? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static struct power_state w100_pwr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* The PLL Fout is determined by (XtalFreq/(M+1)) * ((N_int+1) + (N_fac/8)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* 12.5MHz Crystal PLL Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static struct w100_pll_info xtal_12500000[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /*freq M N_int N_fac tfgoal lock_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) { 50, 0, 1, 0, 0xe0, 56}, /* 50.00 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { 75, 0, 5, 0, 0xde, 37}, /* 75.00 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {100, 0, 7, 0, 0xe0, 28}, /* 100.00 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {125, 0, 9, 0, 0xe0, 22}, /* 125.00 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {150, 0, 11, 0, 0xe0, 17}, /* 150.00 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) { 0, 0, 0, 0, 0, 0}, /* Terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* 14.318MHz Crystal PLL Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct w100_pll_info xtal_14318000[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /*freq M N_int N_fac tfgoal lock_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) { 40, 4, 13, 0, 0xe0, 80}, /* tfgoal guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) { 50, 1, 6, 0, 0xe0, 64}, /* 50.05 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) { 57, 2, 11, 0, 0xe0, 53}, /* tfgoal guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) { 75, 0, 4, 3, 0xe0, 43}, /* 75.08 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {100, 0, 6, 0, 0xe0, 32}, /* 100.10 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) { 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* 16MHz Crystal PLL Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static struct w100_pll_info xtal_16000000[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /*freq M N_int N_fac tfgoal lock_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { 72, 1, 8, 0, 0xe0, 48}, /* tfgoal guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { 80, 1, 9, 0, 0xe0, 13}, /* tfgoal guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) { 95, 1, 10, 7, 0xe0, 38}, /* tfgoal guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) { 96, 1, 11, 0, 0xe0, 36}, /* tfgoal guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) { 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct pll_entries {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct w100_pll_info *pll_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) } w100_pll_tables[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) { 12500000, &xtal_12500000[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) { 14318000, &xtal_14318000[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) { 16000000, &xtal_16000000[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct w100_pll_info *w100_get_xtal_table(unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct pll_entries *pll_entry = w100_pll_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (freq == pll_entry->xtal_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return pll_entry->pll_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pll_entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) } while (pll_entry->xtal_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static unsigned int w100_get_testcount(unsigned int testclk_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) union clk_test_cntl_u clk_test_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Select the test clock source and reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) clk_test_cntl.f.start_check_freq = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) clk_test_cntl.f.testclk_sel = testclk_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) clk_test_cntl.f.tstcount_rst = 0x1; /* set reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) clk_test_cntl.f.tstcount_rst = 0x0; /* clear reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* Run clock test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) clk_test_cntl.f.start_check_freq = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Give the test time to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Return the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) clk_test_cntl.val = readl(remapped_regs + mmCLK_TEST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clk_test_cntl.f.start_check_freq = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return clk_test_cntl.f.test_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int w100_pll_adjust(struct w100_pll_info *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) unsigned int tf80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned int tf20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Initial Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0; /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) w100_pwr_state.pll_cntl.f.pll_reset = 0x0; /* not reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1; /* Hi-Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; /* VCO gain = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; /* VCO frequency range control = off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; /* current offset inside VCO = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Wai Ming 80 percent of VDD 1.3V gives 1.04V, minimum operating voltage is 1.08V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * therefore, commented out the following lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * tf80 meant tf100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* set VCO input = 0.8 * VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) w100_pwr_state.pll_cntl.f.pll_dactal = 0xd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) tf80 = w100_get_testcount(TESTCLK_SRC_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (tf80 >= (pll->tfgoal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* set VCO input = 0.2 * VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) w100_pwr_state.pll_cntl.f.pll_dactal = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) tf20 = w100_get_testcount(TESTCLK_SRC_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (tf20 <= (pll->tfgoal))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return 1; /* Success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) (w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* slow VCO config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) } else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) w100_pwr_state.pll_cntl.f.pll_pvg += 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return 0; /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) } while(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * w100_pll_calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int w100_pll_calibration(struct w100_pll_info *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) status = w100_pll_adjust(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* PLL Reset And Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* set VCO input = 0.5 * VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) w100_pwr_state.pll_cntl.f.pll_dactal = 0xa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) udelay(1); /* reset time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* enable charge pump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0; /* normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* set VCO input = Hi-Z, disable DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) udelay(400); /* lock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* PLL locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int w100_pll_set_clk(struct w100_pll_info *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (w100_pwr_state.auto_mode == 1) /* auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0; /* disable fast to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0; /* disable normal to fast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Set system clock source to XTAL whilst adjusting the PLL! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) status = w100_pll_calibration(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (w100_pwr_state.auto_mode == 1) /* auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x1; /* reenable fast to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x1; /* reenable normal to fast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* freq = target frequency of the PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int w100_set_pll_freq(struct w100fb_par *par, unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct w100_pll_info *pll = par->pll_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (freq == pll->freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return w100_pll_set_clk(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pll++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) } while(pll->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Set up an initial state. Some values/fields set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) here will be overwritten. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static void w100_pwm_setup(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) w100_pwr_state.clk_pin_cntl.f.osc_en = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) w100_pwr_state.clk_pin_cntl.f.osc_gain = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) w100_pwr_state.clk_pin_cntl.f.dont_use_xtalin = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) w100_pwr_state.clk_pin_cntl.f.xtalin_pm_en = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) w100_pwr_state.clk_pin_cntl.f.xtalin_dbl_en = par->mach->xtal_dbl ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) w100_pwr_state.clk_pin_cntl.f.cg_debug = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = 0x0; /* Pfast = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) w100_pwr_state.sclk_cntl.f.sclk_clkon_hys = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0; /* Pslow = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) w100_pwr_state.sclk_cntl.f.disp_cg_ok2switch_en = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) w100_pwr_state.sclk_cntl.f.sclk_force_reg = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) w100_pwr_state.sclk_cntl.f.sclk_force_disp = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) w100_pwr_state.sclk_cntl.f.sclk_force_mc = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) w100_pwr_state.sclk_cntl.f.sclk_force_extmc = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) w100_pwr_state.sclk_cntl.f.sclk_force_cp = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) w100_pwr_state.sclk_cntl.f.sclk_force_e2 = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) w100_pwr_state.sclk_cntl.f.sclk_force_e3 = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) w100_pwr_state.sclk_cntl.f.sclk_force_idct = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) w100_pwr_state.sclk_cntl.f.sclk_force_bist = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) w100_pwr_state.sclk_cntl.f.busy_extend_cp = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) w100_pwr_state.sclk_cntl.f.busy_extend_e2 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) w100_pwr_state.sclk_cntl.f.busy_extend_e3 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) w100_pwr_state.sclk_cntl.f.busy_extend_idct = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) w100_pwr_state.pclk_cntl.f.pclk_src_sel = CLK_SRC_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) w100_pwr_state.pclk_cntl.f.pclk_post_div = 0x1; /* P = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) w100_pwr_state.pclk_cntl.f.pclk_force_disp = 0x0; /* Dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = 0x0; /* M = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = 0x0; /* N = 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) w100_pwr_state.pll_ref_fb_div.f.pll_reset_time = 0x5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) w100_pwr_state.pll_cntl.f.pll_reset = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) w100_pwr_state.pll_cntl.f.pll_pcp = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) w100_pwr_state.pll_cntl.f.pll_dactal = 0x0; /* Hi-Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) w100_pwr_state.pll_cntl.f.pll_conf = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) w100_pwr_state.pwrmgt_cntl.f.pwm_enable = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0x1; /* normal mode (0, 1, 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) w100_pwr_state.pwrmgt_cntl.f.pwm_wakeup_cond = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_cond = 0x1; /* PM4,ENG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_cond = 0x1; /* PM4,ENG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) w100_pwr_state.pwrmgt_cntl.f.pwm_idle_timer = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) w100_pwr_state.pwrmgt_cntl.f.pwm_busy_timer = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) w100_pwr_state.auto_mode = 0; /* manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * Setup the w100 clocks for the specified mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static void w100_init_clocks(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct w100_mode *mode = par->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (mode->pixclk_src == CLK_SRC_PLL || mode->sysclk_src == CLK_SRC_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) w100_set_pll_freq(par, (par->fastpll_mode && mode->fast_pll_freq) ? mode->fast_pll_freq : mode->pll_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) w100_pwr_state.sclk_cntl.f.sclk_src_sel = mode->sysclk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = mode->sysclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = mode->sysclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static void w100_init_lcd(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u32 temp32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct w100_mode *mode = par->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct w100_gen_regs *regs = par->mach->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) union active_h_disp_u active_h_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) union active_v_disp_u active_v_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) union graphic_h_disp_u graphic_h_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) union graphic_v_disp_u graphic_v_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) union crtc_total_u crtc_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* w3200 doesn't like undefined bits being set so zero register values first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) active_h_disp.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) active_h_disp.f.active_h_start=mode->left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) active_h_disp.f.active_h_end=mode->left_margin + mode->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) writel(active_h_disp.val, remapped_regs + mmACTIVE_H_DISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) active_v_disp.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) active_v_disp.f.active_v_start=mode->upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) active_v_disp.f.active_v_end=mode->upper_margin + mode->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) writel(active_v_disp.val, remapped_regs + mmACTIVE_V_DISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) graphic_h_disp.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) graphic_h_disp.f.graphic_h_start=mode->left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) graphic_h_disp.f.graphic_h_end=mode->left_margin + mode->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) writel(graphic_h_disp.val, remapped_regs + mmGRAPHIC_H_DISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) graphic_v_disp.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) graphic_v_disp.f.graphic_v_start=mode->upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) graphic_v_disp.f.graphic_v_end=mode->upper_margin + mode->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) writel(graphic_v_disp.val, remapped_regs + mmGRAPHIC_V_DISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) crtc_total.val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) crtc_total.f.crtc_h_total=mode->left_margin + mode->xres + mode->right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) crtc_total.f.crtc_v_total=mode->upper_margin + mode->yres + mode->lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) writel(crtc_total.val, remapped_regs + mmCRTC_TOTAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) writel(mode->crtc_ss, remapped_regs + mmCRTC_SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) writel(mode->crtc_ls, remapped_regs + mmCRTC_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) writel(mode->crtc_gs, remapped_regs + mmCRTC_GS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) writel(mode->crtc_vpos_gs, remapped_regs + mmCRTC_VPOS_GS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) writel(mode->crtc_rev, remapped_regs + mmCRTC_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) writel(mode->crtc_dclk, remapped_regs + mmCRTC_DCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) writel(mode->crtc_gclk, remapped_regs + mmCRTC_GCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) writel(mode->crtc_goe, remapped_regs + mmCRTC_GOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) writel(mode->crtc_ps1_active, remapped_regs + mmCRTC_PS1_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) writel(regs->lcd_format, remapped_regs + mmLCD_FORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) writel(regs->lcdd_cntl1, remapped_regs + mmLCDD_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) writel(regs->lcdd_cntl2, remapped_regs + mmLCDD_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) writel(regs->genlcd_cntl1, remapped_regs + mmGENLCD_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) writel(regs->genlcd_cntl2, remapped_regs + mmGENLCD_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) writel(regs->genlcd_cntl3, remapped_regs + mmGENLCD_CNTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) writel(0x00000000, remapped_regs + mmCRTC_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) writel(0x00000000, remapped_regs + mmCRTC_FRAME_VPOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) writel(0x00000000, remapped_regs + mmCRTC_DEFAULT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) writel(0x0000FF00, remapped_regs + mmLCD_BACKGROUND_COLOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Hack for overlay in ext memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) temp32 = readl(remapped_regs + mmDISP_DEBUG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) temp32 |= 0xc0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) writel(temp32, remapped_regs + mmDISP_DEBUG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static void w100_setup_memory(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) union mc_ext_mem_location_u extmem_location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) union mc_fb_location_u intmem_location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct w100_mem_info *mem = par->mach->mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct w100_bm_mem_info *bm_mem = par->mach->bm_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!par->extmem_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) w100_suspend(W100_SUSPEND_EXTMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* Map Internal Memory at FB Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) intmem_location.f.mc_fb_start = W100_FB_BASE >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) intmem_location.f.mc_fb_top = (W100_FB_BASE+MEM_INT_SIZE) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* Unmap External Memory - value is *probably* irrelevant but may have meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) to acceleration libraries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) extmem_location.f.mc_ext_mem_start = MEM_EXT_BASE_VALUE >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) extmem_location.f.mc_ext_mem_top = (MEM_EXT_BASE_VALUE-1) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* Map Internal Memory to its default location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) intmem_location.f.mc_fb_start = MEM_INT_BASE_VALUE >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) intmem_location.f.mc_fb_top = (MEM_INT_BASE_VALUE+MEM_INT_SIZE) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* Map External Memory at FB Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) extmem_location.f.mc_ext_mem_start = W100_FB_BASE >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) extmem_location.f.mc_ext_mem_top = (W100_FB_BASE+par->mach->mem->size) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) writel(0x00007800, remapped_regs + mmMC_BIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) writel(mem->ext_cntl, remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) writel(0x00200021, remapped_regs + mmMEM_SDRAM_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) writel(0x80200021, remapped_regs + mmMEM_SDRAM_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) writel(mem->sdram_mode_reg, remapped_regs + mmMEM_SDRAM_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) writel(mem->ext_timing_cntl, remapped_regs + mmMEM_EXT_TIMING_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) writel(mem->io_cntl, remapped_regs + mmMEM_IO_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (bm_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) writel(bm_mem->ext_mem_bw, remapped_regs + mmBM_EXT_MEM_BANDWIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) writel(bm_mem->offset, remapped_regs + mmBM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) writel(bm_mem->ext_timing_ctl, remapped_regs + mmBM_MEM_EXT_TIMING_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) writel(bm_mem->ext_cntl, remapped_regs + mmBM_MEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) writel(bm_mem->io_cntl, remapped_regs + mmBM_MEM_IO_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) writel(bm_mem->config, remapped_regs + mmBM_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static void w100_set_dispregs(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) unsigned long rot=0, divider, offset=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) union graphic_ctrl_u graphic_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* See if the mode has been rotated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (par->xres == par->mode->xres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (par->flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) rot=3; /* 180 degree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) offset=(par->xres * par->yres) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) } /* else 0 degree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) divider = par->mode->pixclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (par->flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) rot=2; /* 270 degree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) offset=par->xres - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) rot=1; /* 90 degree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) offset=par->xres * (par->yres - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) divider = par->mode->pixclk_divider_rotated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) graphic_ctrl.val = 0; /* w32xx doesn't like undefined bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) switch (par->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) case CHIP_ID_W100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) graphic_ctrl.f_w100.color_depth=6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) graphic_ctrl.f_w100.en_crtc=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) graphic_ctrl.f_w100.en_graphic_req=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) graphic_ctrl.f_w100.en_graphic_crtc=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) graphic_ctrl.f_w100.lcd_pclk_on=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) graphic_ctrl.f_w100.lcd_sclk_on=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) graphic_ctrl.f_w100.low_power_on=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) graphic_ctrl.f_w100.req_freq=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) graphic_ctrl.f_w100.portrait_mode=rot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* Zaurus needs this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) switch(par->xres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case 240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case 320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) graphic_ctrl.f_w100.total_req_graphic=0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) case 480:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case 640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) switch(rot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) case 0: /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) case 3: /* 180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) graphic_ctrl.f_w100.low_power_on=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) graphic_ctrl.f_w100.req_freq=5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) case 1: /* 90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case 2: /* 270 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) graphic_ctrl.f_w100.req_freq=4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) graphic_ctrl.f_w100.total_req_graphic=0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) case CHIP_ID_W3200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case CHIP_ID_W3220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) graphic_ctrl.f_w32xx.color_depth=6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) graphic_ctrl.f_w32xx.en_crtc=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) graphic_ctrl.f_w32xx.en_graphic_req=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) graphic_ctrl.f_w32xx.en_graphic_crtc=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) graphic_ctrl.f_w32xx.lcd_pclk_on=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) graphic_ctrl.f_w32xx.lcd_sclk_on=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) graphic_ctrl.f_w32xx.low_power_on=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) graphic_ctrl.f_w32xx.req_freq=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) graphic_ctrl.f_w32xx.total_req_graphic=par->mode->xres >> 1; /* panel xres, not mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) graphic_ctrl.f_w32xx.portrait_mode=rot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Set the pixel clock source and divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) w100_pwr_state.pclk_cntl.f.pclk_src_sel = par->mode->pixclk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) w100_pwr_state.pclk_cntl.f.pclk_post_div = divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) writel(graphic_ctrl.val, remapped_regs + mmGRAPHIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) writel(W100_FB_BASE + ((offset * BITS_PER_PIXEL/8)&~0x03UL), remapped_regs + mmGRAPHIC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) writel((par->xres*BITS_PER_PIXEL/8), remapped_regs + mmGRAPHIC_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * Work out how long the sync pulse lasts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * Value is 1/(time in seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static void calc_hsync(struct w100fb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) unsigned long hsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct w100_mode *mode = par->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) union crtc_ss_u crtc_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (mode->pixclk_src == CLK_SRC_XTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) hsync=par->mach->xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) hsync=((par->fastpll_mode && mode->fast_pll_freq) ? mode->fast_pll_freq : mode->pll_freq)*100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) hsync /= (w100_pwr_state.pclk_cntl.f.pclk_post_div + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) crtc_ss.val = readl(remapped_regs + mmCRTC_SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (crtc_ss.val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) par->hsync_len = hsync / (crtc_ss.f.ss_end-crtc_ss.f.ss_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) par->hsync_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static void w100_suspend(u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) writel(0x7FFF8000, remapped_regs + mmMC_EXT_MEM_LOCATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) writel(0x00FF0000, remapped_regs + mmMC_PERF_MON_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) val = readl(remapped_regs + mmMEM_EXT_TIMING_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) val &= ~(0x00100000); /* bit20=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) val |= 0xFF000000; /* bit31:24=0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) writel(val, remapped_regs + mmMEM_EXT_TIMING_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) val = readl(remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) val &= ~(0x00040000); /* bit18=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) val |= 0x00080000; /* bit19=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) writel(val, remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) udelay(1); /* wait 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (mode == W100_SUSPEND_EXTMEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* CKE: Tri-State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) val = readl(remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) val |= 0x40000000; /* bit30=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) writel(val, remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* CLK: Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) val = readl(remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) val &= ~(0x00000001); /* bit0=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) writel(val, remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) writel(0x00000000, remapped_regs + mmSCLK_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) writel(0x000000BF, remapped_regs + mmCLK_PIN_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) writel(0x00000015, remapped_regs + mmPWRMGT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) val = readl(remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) val |= 0x00000004; /* bit2=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) writel(val, remapped_regs + mmPLL_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) writel(0x00000000, remapped_regs + mmLCDD_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) writel(0x00000000, remapped_regs + mmLCDD_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) writel(0x00000000, remapped_regs + mmGENLCD_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) writel(0x00000000, remapped_regs + mmGENLCD_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) writel(0x00000000, remapped_regs + mmGENLCD_CNTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) val = readl(remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) val |= 0xF0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) val &= ~(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) writel(val, remapped_regs + mmMEM_EXT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) writel(0x0000001d, remapped_regs + mmPWRMGT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void w100_vsync(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) int timeout = 30000; /* VSync timeout = 30[ms] > 16.8[ms] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) tmp = readl(remapped_regs + mmACTIVE_V_DISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* set vline pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) writel((tmp >> 16) & 0x3ff, remapped_regs + mmDISP_INT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* disable vline irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) tmp = readl(remapped_regs + mmGEN_INT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) tmp &= ~0x00000002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) writel(tmp, remapped_regs + mmGEN_INT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* clear vline irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* enable vline irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) writel((tmp | 0x00000002), remapped_regs + mmGEN_INT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* clear vline irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) while(timeout > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (readl(remapped_regs + mmGEN_INT_STATUS) & 0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* disable vline irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) writel(tmp, remapped_regs + mmGEN_INT_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* clear vline irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static struct platform_driver w100fb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .probe = w100fb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .remove = w100fb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .suspend = w100fb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .resume = w100fb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .name = "w100fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .dev_groups = w100fb_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) module_platform_driver(w100fb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MODULE_DESCRIPTION("ATI Imageon w100 framebuffer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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