^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/via-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/via_i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "global.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static const struct IODATA common_init_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Index, Mask, Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Set panel power sequence timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {0x10, 0xC0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {0x0B, 0xFF, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {0x0C, 0xFF, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {0x0D, 0xFF, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {0x0E, 0xFF, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {0x0F, 0xFF, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* LVDS output power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {0x09, 0xA0, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* turn on back light */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {0x10, 0x33, 0x13}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Index, Mask, Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct IODATA dual_channel_enable_data = {0x08, 0xF0, 0xE0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct IODATA single_channel_enable_data = {0x08, 0xF0, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct IODATA dithering_enable_data = {0x0A, 0x70, 0x50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct IODATA dithering_disable_data = {0x0A, 0x70, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct IODATA vdd_on_data = {0x10, 0x20, 0x20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct IODATA vdd_off_data = {0x10, 0x20, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) viafb_i2c_readbyte(plvds_chip_info->i2c_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) plvds_chip_info->lvds_chip_slave_addr, index, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *plvds_setting_info, struct lvds_chip_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *plvds_chip_info, struct IODATA io_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int index, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) index = io_data.Index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) data = viafb_gpio_i2c_read_lvds(plvds_setting_info, plvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) data = (data & (~io_data.Mask)) | io_data.Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) viafb_i2c_writebyte(plvds_chip_info->i2c_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) plvds_chip_info->lvds_chip_slave_addr, index, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void viafb_init_lvds_vt1636(struct lvds_setting_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int reg_num, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Common settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg_num = ARRAY_SIZE(common_init_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for (i = 0; i < reg_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) plvds_chip_info, common_init_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Input Data Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (plvds_setting_info->device_lcd_dualedge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) plvds_chip_info, dual_channel_enable_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) plvds_chip_info, single_channel_enable_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (plvds_setting_info->LCDDithering)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) plvds_chip_info, dithering_enable_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) plvds_chip_info, dithering_disable_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void viafb_enable_lvds_vt1636(struct lvds_setting_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct lvds_chip_information *plvds_chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) vdd_on_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void viafb_disable_lvds_vt1636(struct lvds_setting_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct lvds_chip_information *plvds_chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) vdd_off_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool viafb_lvds_identify_vt1636(u8 i2c_adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 Buffer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEBUG_MSG(KERN_INFO "viafb_lvds_identify_vt1636.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Sense VT1636 LVDS Transmiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) VT1636_LVDS_I2C_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Check vendor ID first: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x00, &Buffer[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x01, &Buffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!((Buffer[0] == 0x06) && (Buffer[1] == 0x11)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Check Chip ID: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x02, &Buffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x03, &Buffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if ((Buffer[0] == 0x45) && (Buffer[1] == 0x33)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) VT1636_LVDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int get_clk_range_index(u32 Clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (Clk < DPA_CLK_30M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return DPA_CLK_RANGE_30M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else if (Clk < DPA_CLK_50M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return DPA_CLK_RANGE_30_50M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else if (Clk < DPA_CLK_70M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return DPA_CLK_RANGE_50_70M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else if (Clk < DPA_CLK_100M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return DPA_CLK_RANGE_70_100M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else if (Clk < DPA_CLK_150M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return DPA_CLK_RANGE_100_150M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return DPA_CLK_RANGE_150M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void set_dpa_vt1636(struct lvds_setting_information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct IODATA io_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) io_data.Index = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) io_data.Mask = 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) plvds_chip_info, io_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) io_data.Index = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) io_data.Mask = 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) io_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void viafb_vt1636_patch_skew_on_vt3324(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct lvds_setting_information *plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct lvds_chip_information *plvds_chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct VT1636_DPA_SETTING dpa = {0x00, 0x00}, dpa_16x12 = {0x0B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *pdpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Graphics DPA settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) index = get_clk_range_index(plvds_setting_info->vclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) viafb_set_dpa_gfx(plvds_chip_info->output_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &GFX_DPA_SETTING_TBL_VT3324[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* LVDS Transmitter DPA settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (plvds_setting_info->lcd_panel_hres == 1600 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) plvds_setting_info->lcd_panel_vres == 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pdpa = &dpa_16x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pdpa = &dpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) set_dpa_vt1636(plvds_setting_info, plvds_chip_info, pdpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void viafb_vt1636_patch_skew_on_vt3327(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct lvds_setting_information *plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct lvds_chip_information *plvds_chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct VT1636_DPA_SETTING dpa = {0x00, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Graphics DPA settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) index = get_clk_range_index(plvds_setting_info->vclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) viafb_set_dpa_gfx(plvds_chip_info->output_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &GFX_DPA_SETTING_TBL_VT3327[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* LVDS Transmitter DPA settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) set_dpa_vt1636(plvds_setting_info, plvds_chip_info, &dpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void viafb_vt1636_patch_skew_on_vt3364(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct lvds_setting_information *plvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct lvds_chip_information *plvds_chip_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3364.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Graphics DPA settings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) index = get_clk_range_index(plvds_setting_info->vclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) viafb_set_dpa_gfx(plvds_chip_info->output_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) &GFX_DPA_SETTING_TBL_VT3364[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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