^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "global.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) DVP1Driving, DFPHigh, DFPLow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SR65, CR97, CR99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* LCK/VCK < 30000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* 30000000 < LCK/VCK < 50000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* 50000000 < LCK/VCK < 70000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* 70000000 < LCK/VCK < 100000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* 100000000 < LCK/VCK < 15000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* 15000000 < LCK/VCK will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DVP1Driving, DFPHigh, DFPLow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SR65, CR97, CR99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* LCK/VCK < 30000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* 30000000 < LCK/VCK < 50000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 50000000 < LCK/VCK < 70000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* 70000000 < LCK/VCK < 100000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* 100000000 < LCK/VCK < 15000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 15000000 < LCK/VCK will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* For VT3364: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DVP1Driving, DFPHigh, DFPLow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SR65, CR97, CR99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* LCK/VCK < 30000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 30000000 < LCK/VCK < 50000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* 50000000 < LCK/VCK < 70000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* 70000000 < LCK/VCK < 100000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* 100000000 < LCK/VCK < 15000000 will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 15000000 < LCK/VCK will use this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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