^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __SHARE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __SHARE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "via_modesetting.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Define Bit Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BIT0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BIT1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BIT2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BIT3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BIT4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BIT5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BIT6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BIT7 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Video Memory Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VIDEO_MEMORY_SIZE_16M 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Lengths of the VPIT structure arrays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define StdCR 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define StdSR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define StdGR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define StdAR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PatchCR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Display path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IGA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IGA2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Define Color Depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MODE_8BPP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MODE_16BPP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MODE_32BPP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GR20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GR21 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GR22 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Sequencer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SR01 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SR10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SR12 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SR15 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SR16 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SR17 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SR18 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SR1B 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SR1A 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SR1C 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SR1D 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SR1E 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SR1F 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SR20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SR21 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SR22 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SR2A 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SR2D 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SR2E 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SR30 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SR39 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SR3D 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SR3E 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SR3F 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SR40 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SR43 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SR44 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SR45 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SR46 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SR47 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SR48 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SR49 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SR4A 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SR4B 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SR4C 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SR52 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SR57 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SR58 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SR59 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SR5D 0x5D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SR5E 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SR65 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* CRT Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CR00 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CR01 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CR02 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CR03 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CR04 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CR05 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CR06 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CR07 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CR08 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CR09 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CR0A 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CR0B 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CR0C 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CR0D 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CR0E 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CR0F 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CR10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CR11 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CR12 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CR13 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CR14 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CR15 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CR16 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CR17 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CR18 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Extend CRT Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CR30 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CR31 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CR32 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CR33 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CR34 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CR35 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CR36 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CR37 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CR38 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CR39 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CR3A 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CR3B 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CR3C 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CR3D 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CR3E 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CR3F 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CR40 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CR41 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CR42 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CR43 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CR44 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CR45 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CR46 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CR47 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CR48 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CR49 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CR4A 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CR4B 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CR4C 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CR4D 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CR4E 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CR4F 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CR50 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CR51 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CR52 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CR53 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CR54 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CR55 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CR56 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CR57 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CR58 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CR59 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CR5A 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CR5B 0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CR5C 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CR5D 0x5D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CR5E 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CR5F 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CR60 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CR61 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CR62 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CR63 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CR64 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CR65 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CR66 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CR67 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CR68 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CR69 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CR6A 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CR6B 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CR6C 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CR6D 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CR6E 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CR6F 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CR70 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CR71 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CR72 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CR73 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CR74 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CR75 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CR76 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CR77 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CR78 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CR79 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CR7A 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CR7B 0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CR7C 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CR7D 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CR7E 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CR7F 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CR80 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CR81 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CR82 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CR83 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CR84 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CR85 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CR86 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CR87 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CR88 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CR89 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CR8A 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CR8B 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CR8C 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CR8D 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CR8E 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CR8F 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CR90 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CR91 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CR92 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CR93 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CR94 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CR95 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CR96 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CR97 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CR98 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CR99 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CR9A 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CR9B 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CR9C 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CR9D 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CR9E 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CR9F 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CRA0 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CRA1 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CRA2 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CRA3 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CRD2 0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CRD3 0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CRD4 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* LUT Table*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define LUT_DATA 0x3C9 /* DACDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define LUT_INDEX_READ 0x3C7 /* DACRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define LUT_INDEX_WRITE 0x3C8 /* DACWX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DACMASK 0x3C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Definition Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DEVICE_CRT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DEVICE_DVI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DEVICE_LCD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Device output interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define INTERFACE_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define INTERFACE_ANALOG_RGB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define INTERFACE_DVP0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define INTERFACE_DVP1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define INTERFACE_DFP_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define INTERFACE_DFP_LOW 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define INTERFACE_DFP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define INTERFACE_LVDS0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define INTERFACE_LVDS1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define INTERFACE_LVDS0LVDS1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define INTERFACE_TMDS 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HW_LAYOUT_LCD_ONLY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HW_LAYOUT_DVI_ONLY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HW_LAYOUT_LCD_DVI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HW_LAYOUT_LCD1_LCD2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Definition CRTC Timing Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define H_TOTAL_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define H_ADDR_INDEX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define H_BLANK_START_INDEX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define H_BLANK_END_INDEX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define H_SYNC_START_INDEX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define H_SYNC_END_INDEX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define V_TOTAL_INDEX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define V_ADDR_INDEX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define V_BLANK_START_INDEX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define V_BLANK_END_INDEX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define V_SYNC_START_INDEX 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define V_SYNC_END_INDEX 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define H_TOTAL_SHADOW_INDEX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define H_BLANK_END_SHADOW_INDEX 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define V_TOTAL_SHADOW_INDEX 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define V_ADDR_SHADOW_INDEX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define V_BLANK_SATRT_SHADOW_INDEX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define V_BLANK_END_SHADOW_INDEX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define V_SYNC_SATRT_SHADOW_INDEX 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define V_SYNC_END_SHADOW_INDEX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* LCD display method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LCD_EXPANDSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LCD_CENTERING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* LCD mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define LCD_OPENLDI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define LCD_SPWG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct crt_mode_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int refresh_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int h_sync_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int v_sync_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct via_display_timing crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct io_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif /* __SHARE_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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