^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __HW_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __HW_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "viamode.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "global.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "via_modesetting.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define viafb_read_reg(p, i) via_read_reg(p, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define viafb_write_reg(i, p, d) via_write_reg(p, i, d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* VIA output devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIA_LDVP0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VIA_LDVP1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VIA_DVP0 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIA_CRT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VIA_DVP1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VIA_LVDS1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VIA_LVDS2 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* VIA output device power states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VIA_STATE_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VIA_STATE_STANDBY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VIA_STATE_SUSPEND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VIA_STATE_OFF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* VIA output device sync polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIA_HSYNC_NEGATIVE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIA_VSYNC_NEGATIVE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Definition IGA2 Design Method of CRTC Shadow Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Define Register Number for IGA2 Shadow CRTC Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* location: {CR6D,0,7},{CR71,3,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* location: {CR6E,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* location: {CR6F,0,7},{CR71,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* location: {CR70,0,7},{CR71,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IGA2_SHADOW_VER_ADDR_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* location: {CR72,0,7},{CR74,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* location: {CR73,0,7},{CR74,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* location: {CR75,0,7},{CR76,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* location: {CR76,0,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Define Fetch Count Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* location: {SR1C,0,7},{SR1D,0,1} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IGA1_FETCH_COUNT_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* 16 bytes alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IGA1_FETCH_COUNT_ALIGN_BYTE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* x: H resolution, y: color depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IGA1_FETCH_COUNT_PATCH_VALUE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IGA1_FETCH_COUNT_FORMULA(x, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* location: {CR65,0,7},{CR67,2,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IGA2_FETCH_COUNT_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IGA2_FETCH_COUNT_ALIGN_BYTE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IGA2_FETCH_COUNT_PATCH_VALUE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IGA2_FETCH_COUNT_FORMULA(x, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Staring Address*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IGA1_STARTING_ADDR_REG_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IGA2_STARTING_ADDR_REG_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Define Display OFFSET*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* These value are by HW suggested value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define K800_IGA1_FIFO_MAX_DEPTH 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define K800_IGA1_FIFO_THRESHOLD 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define K800_IGA1_FIFO_HIGH_THRESHOLD 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* because HW only 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define K800_IGA2_FIFO_MAX_DEPTH 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define K800_IGA2_FIFO_THRESHOLD 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define K800_IGA2_FIFO_HIGH_THRESHOLD 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define P880_IGA1_FIFO_MAX_DEPTH 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define P880_IGA1_FIFO_THRESHOLD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define P880_IGA1_FIFO_HIGH_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* because HW only 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define P880_IGA2_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define P880_IGA2_FIFO_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define P880_IGA2_FIFO_HIGH_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* VT3314 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CN700_IGA1_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CN700_IGA1_FIFO_THRESHOLD 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) because HW only 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CN700_IGA2_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CN700_IGA2_FIFO_THRESHOLD 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* For VT3324, these values are suggested by HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CX700_IGA1_FIFO_MAX_DEPTH 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CX700_IGA1_FIFO_THRESHOLD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* location: {SR22,0,4} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CX700_IGA2_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CX700_IGA2_FIFO_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* VT3336 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define K8M890_IGA1_FIFO_MAX_DEPTH 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define K8M890_IGA1_FIFO_THRESHOLD 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* location: {SR22,0,4}. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define K8M890_IGA2_FIFO_MAX_DEPTH 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define K8M890_IGA2_FIFO_THRESHOLD 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* VT3327 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define P4M890_IGA1_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define P4M890_IGA1_FIFO_THRESHOLD 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* location: {SR22,0,4}. (32/4) =8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define P4M890_IGA2_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define P4M890_IGA2_FIFO_THRESHOLD 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* VT3364 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define P4M900_IGA1_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define P4M900_IGA1_FIFO_THRESHOLD 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* location: {SR22,0,4}. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define P4M900_IGA2_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define P4M900_IGA2_FIFO_THRESHOLD 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* For VT3353, these values are suggested by HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* location: {SR17,0,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define VX800_IGA1_FIFO_MAX_DEPTH 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* location: {SR16,0,5},{SR16,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VX800_IGA1_FIFO_THRESHOLD 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* location: {SR18,0,5},{SR18,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* location: {SR22,0,4} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VX800_IGA2_FIFO_MAX_DEPTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* location: {CR68,0,3},{CR95,4,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VX800_IGA2_FIFO_THRESHOLD 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* location: {CR92,0,3},{CR95,0,2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* location: {CR94,0,6} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* For VT3409 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VX855_IGA1_FIFO_MAX_DEPTH 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VX855_IGA1_FIFO_THRESHOLD 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VX855_IGA2_FIFO_MAX_DEPTH 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define VX855_IGA2_FIFO_THRESHOLD 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* For VT3410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VX900_IGA1_FIFO_MAX_DEPTH 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define VX900_IGA1_FIFO_THRESHOLD 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define VX900_IGA1_FIFO_HIGH_THRESHOLD 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define VX900_IGA2_FIFO_MAX_DEPTH 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define VX900_IGA2_FIFO_THRESHOLD 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define VX900_IGA2_FIFO_HIGH_THRESHOLD 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IGA1_FIFO_THRESHOLD_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IGA2_FIFO_THRESHOLD_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* LCD Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* 500 ms = 500000 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LCD_POWER_SEQ_TD0 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* 50 ms = 50000 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LCD_POWER_SEQ_TD1 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* 0 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LCD_POWER_SEQ_TD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* 210 ms = 210000 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define LCD_POWER_SEQ_TD3 210000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLE266_POWER_SEQ_UNIT 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define K800_POWER_SEQ_UNIT 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* 2^13 * (1/14.31818M) = 572.1 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define P880_POWER_SEQ_UNIT 572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* location: {CR8B,0,7},{CR8F,0,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define LCD_POWER_SEQ_TD0_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* location: {CR8C,0,7},{CR8F,4,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define LCD_POWER_SEQ_TD1_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* location: {CR8D,0,7},{CR90,0,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define LCD_POWER_SEQ_TD2_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* location: {CR8E,0,7},{CR90,4,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define LCD_POWER_SEQ_TD3_REG_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* LCD Scaling factor*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* x: indicate setting horizontal size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* y: indicate panel horizontal size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Horizontal scaling factor 10 bits (2^10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Vertical scaling factor 10 bits (2^10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Horizontal scaling factor 10 bits (2^12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Vertical scaling factor 10 bits (2^11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define LCD_HOR_SCALING_FACTOR_REG_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define LCD_VER_SCALING_FACTOR_REG_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* location: {CR77,0,7},{CR79,4,5} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* location: {CR78,0,7},{CR79,6,7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct io_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 start_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 end_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*****************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ** Define IGA2 Shadow Display Timing ****
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* IGA2 Shadow Horizontal Total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct iga2_shadow_hor_total {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* IGA2 Shadow Horizontal Blank End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct iga2_shadow_hor_blank_end {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* IGA2 Shadow Vertical Total */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct iga2_shadow_ver_total {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* IGA2 Shadow Vertical Addressable Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct iga2_shadow_ver_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* IGA2 Shadow Vertical Blank Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct iga2_shadow_ver_blank_start {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* IGA2 Shadow Vertical Blank End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct iga2_shadow_ver_blank_end {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* IGA2 Shadow Vertical Sync Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct iga2_shadow_ver_sync_start {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* IGA2 Shadow Vertical Sync End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct iga2_shadow_ver_sync_end {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* IGA1 Fetch Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct iga1_fetch_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* IGA2 Fetch Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct iga2_fetch_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct fetch_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct iga1_fetch_count iga1_fetch_count_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct iga2_fetch_count iga2_fetch_count_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Starting Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct iga1_starting_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct iga2_starting_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct starting_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct iga1_starting_addr iga1_starting_addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct iga2_starting_addr iga2_starting_addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* LCD Power Sequence Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct lcd_pwd_seq_td0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct lcd_pwd_seq_td1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct lcd_pwd_seq_td2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct lcd_pwd_seq_td3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct _lcd_pwd_seq_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct lcd_pwd_seq_td0 td0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct lcd_pwd_seq_td1 td1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct lcd_pwd_seq_td2 td2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct lcd_pwd_seq_td3 td3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* LCD Scaling Factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct _lcd_hor_scaling_factor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct _lcd_ver_scaling_factor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct _lcd_scaling_factor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct pll_limit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u16 multiplier_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 multiplier_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 rshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct rgbLUT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 green;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct lcd_pwd_seq_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u16 td0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u16 td1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u16 td2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u16 td3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Display FIFO Relation Registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct iga1_fifo_depth_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct iga1_fifo_threshold_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct iga1_fifo_high_threshold_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct iga1_display_queue_expire_num {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct iga2_fifo_depth_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct iga2_fifo_threshold_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct iga2_fifo_high_threshold_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct iga2_display_queue_expire_num {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct fifo_depth_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct fifo_threshold_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct fifo_high_threshold_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct iga1_fifo_high_threshold_select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) iga1_fifo_high_threshold_select_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct iga2_fifo_high_threshold_select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) iga2_fifo_high_threshold_select_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct display_queue_expire_num {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct iga1_display_queue_expire_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) iga1_display_queue_expire_num_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct iga2_display_queue_expire_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) iga2_display_queue_expire_num_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct iga2_shadow_crtc_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct iga2_shadow_hor_total hor_total_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct iga2_shadow_ver_total ver_total_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct iga2_shadow_ver_addr ver_addr_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define CLE266_FUNCTION3 0x3123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define KM400_FUNCTION3 0x3205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define CN400_FUNCTION2 0x2259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define CN400_FUNCTION3 0x3259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* support VT3314 chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define CN700_FUNCTION2 0x2314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define CN700_FUNCTION3 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* VT3324 chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define CX700_FUNCTION2 0x2324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define CX700_FUNCTION3 0x3324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* VT3204 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define KM800_FUNCTION3 0x3204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* VT3336 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define KM890_FUNCTION3 0x3336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* VT3327 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define P4M890_FUNCTION3 0x3327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* VT3293 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define CN750_FUNCTION3 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* VT3364 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define P4M900_FUNCTION3 0x3364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* VT3353 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define VX800_FUNCTION3 0x3353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* VT3409 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define VX855_FUNCTION3 0x3409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* VT3410 chipset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define VX900_FUNCTION3 0x3410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct IODATA {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 Index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 Mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct pci_device_id_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 chip_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct via_device_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) extern int viafb_SAMM_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) extern int viafb_dual_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) extern int viafb_LCD2_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) extern int viafb_LCD_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) extern int viafb_DVI_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) extern int viafb_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct via_display_timing var_to_timing(const struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u16 cxres, u16 cyres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u16 cxres, u16 cyres, int iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) void viafb_set_vclock(u32 CLK, int set_iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) void viafb_load_reg(int timing_value, int viafb_load_reg_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct io_register *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int io_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) void via_set_source(u32 devices, u8 iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) void via_set_state(u32 devices, u8 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) void via_set_sync_polarity(u32 devices, u8 polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 via_parse_odev(char *input, char **end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) void via_odev_to_seq(struct seq_file *m, u32 odev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) void init_ad9389(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Access I/O Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void viafb_lock_crt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) void viafb_unlock_crt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *p_gfx_dpa_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int viafb_setmode(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const struct fb_videomode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void viafb_init_chip_info(int chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void viafb_init_dac(int set_iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int viafb_get_refresh(int hres, int vres, u32 float_refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) void viafb_update_device_setting(int hres, int vres, int bpp, int flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) void viafb_set_iga_path(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #endif /* __HW_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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