^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/via-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "global.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "via_clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static struct pll_limit cle266_pll_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {19, 19, 4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {26, 102, 5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {53, 112, 6, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {41, 100, 7, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {83, 108, 8, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {87, 118, 9, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {95, 115, 12, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {108, 108, 13, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {83, 83, 17, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {67, 98, 20, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {121, 121, 24, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {99, 99, 29, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {33, 33, 3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {15, 23, 4, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {37, 121, 5, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {82, 82, 6, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {31, 84, 7, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {83, 83, 8, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {76, 127, 9, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {33, 121, 4, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {91, 118, 5, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {83, 109, 6, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {90, 90, 7, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {93, 93, 2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {53, 53, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {73, 117, 4, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {101, 127, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {99, 99, 7, 3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct pll_limit k800_pll_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {22, 22, 2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {28, 28, 3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {81, 112, 3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {86, 166, 4, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {109, 153, 5, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {66, 116, 3, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {93, 137, 4, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {117, 208, 5, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {30, 30, 2, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {69, 125, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {89, 161, 4, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {121, 208, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {66, 66, 2, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {85, 85, 3, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {141, 161, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {177, 177, 5, 4}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct pll_limit cx700_pll_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {98, 98, 3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {86, 86, 4, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {109, 208, 5, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {68, 68, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {95, 116, 3, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {93, 166, 4, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {110, 206, 5, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {174, 174, 7, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {82, 109, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {117, 161, 4, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {112, 208, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {141, 202, 5, 4}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct pll_limit vx855_pll_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {86, 86, 4, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {108, 208, 5, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {110, 208, 5, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {83, 112, 3, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {103, 161, 4, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {112, 209, 5, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {142, 161, 4, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {141, 176, 5, 4}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* according to VIA Technologies these values are based on experiment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct io_reg scaling_parameters[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct io_reg common_vga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [1] vertical display end (bit 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [2] vertical retrace start (bit 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [3] start vertical blanking (bit 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [4] line compare (bit 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [5] vertical total (bit 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [6] vertical display end (bit 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [7] vertical retrace start (bit 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [5-6] byte panning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [5] start vertical blanking (bit 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [6] line compare (bit 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [7] scan doubling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [5] cursor disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [5-6] cursor skew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [6] memory refresh bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [7] CRTC register protect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [5] divide memory address clock by 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [6] double word addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [2] divide scan line clock by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [3] divide memory address clock by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [5] address wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [6] byte mode select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [7] sync enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct fifo_depth_select display_fifo_depth_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* IGA1 FIFO Depth_Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* IGA2 FIFO Depth_Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct fifo_threshold_select fifo_threshold_select_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* IGA1 FIFO Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* IGA2 FIFO Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* IGA1 FIFO High Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* IGA2 FIFO High Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct display_queue_expire_num display_queue_expire_num_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* IGA1 Display Queue Expire Num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* IGA2 Display Queue Expire Num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Definition Fetch Count Registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct fetch_count fetch_count_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* IGA1 Fetch Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* IGA2 Fetch Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct rgbLUT palLUT_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* {R,G,B} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Index 0x00~0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Index 0x04~0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Index 0x08~0x0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Index 0x0C~0x0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Index 0x10~0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Index 0x14~0x17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Index 0x18~0x1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Index 0x1C~0x1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Index 0x20~0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Index 0x24~0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Index 0x28~0x2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x2F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Index 0x2C~0x2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Index 0x30~0x33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Index 0x34~0x37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Index 0x38~0x3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Index 0x3C~0x3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Index 0x40~0x43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Index 0x44~0x47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Index 0x48~0x4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Index 0x4C~0x4F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Index 0x50~0x53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Index 0x54~0x57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Index 0x58~0x5B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x2D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Index 0x5C~0x5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x2D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Index 0x60~0x63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x3A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Index 0x64~0x67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Index 0x68~0x6B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Index 0x6C~0x6F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Index 0x70~0x73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Index 0x74~0x77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Index 0x78~0x7B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Index 0x7C~0x7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Index 0x80~0x83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Index 0x84~0x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Index 0x88~0x8B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Index 0x8C~0x8F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Index 0x90~0x93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Index 0x94~0x97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Index 0x98~0x9B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Index 0x9C~0x9F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Index 0xA0~0xA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Index 0xA4~0xA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Index 0xA8~0xAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Index 0xAC~0xAF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Index 0xB0~0xB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Index 0xB4~0xB7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Index 0xB8~0xBB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Index 0xBC~0xBF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Index 0xC0~0xC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Index 0xC4~0xC7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Index 0xC8~0xCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Index 0xCC~0xCF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Index 0xD0~0xD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Index 0xD4~0xD7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Index 0xD8~0xDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Index 0xDC~0xDF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Index 0xE0~0xE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Index 0xE4~0xE7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Index 0xE8~0xEB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Index 0xEC~0xEF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Index 0xF0~0xF3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Index 0xF4~0xF7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Index 0xF8~0xFB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Index 0xFC~0xFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct via_device_mapping device_mapping[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {VIA_LDVP0, "LDVP0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {VIA_LDVP1, "LDVP1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {VIA_DVP0, "DVP0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {VIA_CRT, "CRT"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {VIA_DVP1, "DVP1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {VIA_LVDS1, "LVDS1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {VIA_LVDS2, "LVDS2"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* structure with function pointers to support clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct via_clock clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void load_fix_bit_crtc_reg(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void init_gfx_chip_info(int chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void init_tmds_chip_info(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void init_lvds_chip_info(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void device_screen_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void device_screen_on(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void set_display_channel(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void device_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void device_on(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static void enable_second_display_channel(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void disable_second_display_channel(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void viafb_lock_crt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void viafb_unlock_crt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) outb(index, LUT_INDEX_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) outb(r, LUT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) outb(g, LUT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) outb(b, LUT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static u32 get_dvi_devices(int output_interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) switch (output_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case INTERFACE_DVP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return VIA_DVP0 | VIA_LDVP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case INTERFACE_DVP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return VIA_LDVP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return VIA_DVP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case INTERFACE_DFP_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return VIA_LVDS2 | VIA_DVP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case INTERFACE_DFP_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return VIA_DVP1 | VIA_LVDS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case INTERFACE_TMDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return VIA_LVDS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static u32 get_lcd_devices(int output_interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) switch (output_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case INTERFACE_DVP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return VIA_DVP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case INTERFACE_DVP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return VIA_DVP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case INTERFACE_DFP_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return VIA_LVDS2 | VIA_DVP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case INTERFACE_DFP_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return VIA_LVDS1 | VIA_DVP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case INTERFACE_DFP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return VIA_LVDS1 | VIA_LVDS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case INTERFACE_LVDS0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case INTERFACE_LVDS0LVDS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return VIA_LVDS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case INTERFACE_LVDS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return VIA_LVDS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*Set IGA path for each device*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void viafb_set_iga_path(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int crt_iga_path = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (viafb_SAMM_ON == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (viafb_CRT_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (viafb_primary_dev == CRT_Device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) crt_iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) crt_iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (viafb_primary_dev == DVI_Device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) viaparinfo->tmds_setting_info->iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) viaparinfo->tmds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (viafb_LCD_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (viafb_primary_dev == LCD_Device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (viafb_dual_fb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (viaparinfo->chip_info->gfx_chip_name ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) UNICHROME_CLE266)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) viaparinfo->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) lvds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) crt_iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) viaparinfo->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tmds_setting_info->iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) viaparinfo->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) lvds_setting_info->iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) viaparinfo->lvds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (viafb_LCD2_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (LCD2_Device == viafb_primary_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) viaparinfo->lvds_setting_info2->iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) viaparinfo->lvds_setting_info2->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) viafb_SAMM_ON = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (viafb_CRT_ON && viafb_LCD_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) crt_iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) viaparinfo->lvds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) } else if (viafb_CRT_ON && viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) crt_iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) viaparinfo->tmds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else if (viafb_LCD_ON && viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) viaparinfo->tmds_setting_info->iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) viaparinfo->lvds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else if (viafb_LCD_ON && viafb_LCD2_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) viaparinfo->lvds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) viaparinfo->lvds_setting_info2->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else if (viafb_CRT_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) crt_iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else if (viafb_LCD_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) viaparinfo->lvds_setting_info->iga_path = IGA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else if (viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) viaparinfo->tmds_setting_info->iga_path = IGA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) viaparinfo->shared->iga1_devices = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) viaparinfo->shared->iga2_devices = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (viafb_CRT_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (crt_iga_path == IGA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) viaparinfo->shared->iga1_devices |= VIA_CRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) viaparinfo->shared->iga2_devices |= VIA_CRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (viaparinfo->tmds_setting_info->iga_path == IGA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) viaparinfo->shared->iga1_devices |= get_dvi_devices(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tmds_chip_info.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) viaparinfo->shared->iga2_devices |= get_dvi_devices(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tmds_chip_info.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (viafb_LCD_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (viaparinfo->lvds_setting_info->iga_path == IGA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) viaparinfo->shared->iga1_devices |= get_lcd_devices(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) lvds_chip_info.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) viaparinfo->shared->iga2_devices |= get_lcd_devices(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) lvds_chip_info.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (viafb_LCD2_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) viaparinfo->shared->iga1_devices |= get_lcd_devices(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) lvds_chip_info2.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) viaparinfo->shared->iga2_devices |= get_lcd_devices(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) lvds_chip_info2.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* looks like the OLPC has its display wired to DVP1 and LVDS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (machine_is_olpc())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) outb(0xFF, 0x3C6); /* bit mask of palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) outb(index, 0x3C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) outb(red, 0x3C9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) outb(green, 0x3C9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) outb(blue, 0x3C9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) set_color_register(index, red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) set_color_register(index, red, green, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void set_source_common(u8 index, u8 offset, u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 value, mask = 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) switch (iga) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case IGA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case IGA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) value = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) via_write_reg_mask(VIACR, index, value, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void set_crt_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) switch (iga) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case IGA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case IGA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) value = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) via_write_reg_mask(VIASR, 0x16, value, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static inline void set_ldvp0_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) set_source_common(0x6C, 7, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static inline void set_ldvp1_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) set_source_common(0x93, 7, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static inline void set_dvp0_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) set_source_common(0x96, 4, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static inline void set_dvp1_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) set_source_common(0x9B, 4, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static inline void set_lvds1_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) set_source_common(0x99, 4, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static inline void set_lvds2_source(u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) set_source_common(0x97, 4, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) void via_set_source(u32 devices, u8 iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (devices & VIA_LDVP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) set_ldvp0_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (devices & VIA_LDVP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) set_ldvp1_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (devices & VIA_DVP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) set_dvp0_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (devices & VIA_CRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) set_crt_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (devices & VIA_DVP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) set_dvp1_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (devices & VIA_LVDS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) set_lvds1_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (devices & VIA_LVDS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) set_lvds2_source(iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static void set_crt_state(u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case VIA_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case VIA_STATE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) value = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case VIA_STATE_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) value = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case VIA_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) value = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) via_write_reg_mask(VIACR, 0x36, value, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void set_dvp0_state(u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case VIA_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) value = 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case VIA_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void set_dvp1_state(u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case VIA_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) value = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case VIA_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) via_write_reg_mask(VIASR, 0x1E, value, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void set_lvds1_state(u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case VIA_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) value = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case VIA_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) via_write_reg_mask(VIASR, 0x2A, value, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void set_lvds2_state(u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case VIA_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) value = 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case VIA_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) void via_set_state(u32 devices, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) TODO: Can we enable/disable these devices? How?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (devices & VIA_LDVP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (devices & VIA_LDVP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (devices & VIA_DVP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) set_dvp0_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (devices & VIA_CRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) set_crt_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (devices & VIA_DVP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) set_dvp1_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (devices & VIA_LVDS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) set_lvds1_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (devices & VIA_LVDS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) set_lvds2_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) void via_set_sync_polarity(u32 devices, u8 polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) printk(KERN_WARNING "viafb: Unsupported polarity: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (devices & VIA_CRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) via_write_misc_reg_mask(polarity << 6, 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (devices & VIA_DVP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (devices & VIA_LVDS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (devices & VIA_LVDS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 via_parse_odev(char *input, char **end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) char *ptr = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 odev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) bool next = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) while (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) next = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) len = strlen(device_mapping[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!strncmp(ptr, device_mapping[i].name, len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) odev |= device_mapping[i].device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ptr += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (*ptr == ',') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) next = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *end = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return odev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) void via_odev_to_seq(struct seq_file *m, u32 odev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (odev & device_mapping[i].device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) seq_putc(m, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) seq_puts(m, device_mapping[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static void load_fix_bit_crtc_reg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) viafb_unlock_crt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* always set to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* line compare should set all bits = 1 (extend modes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* line compare should set all bits = 1 (extend modes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) viafb_lock_crt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* If K8M800, enable Prefetch Mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) void viafb_load_reg(int timing_value, int viafb_load_reg_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct io_register *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int io_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int bit_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int shift_next_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int start_index, end_index, cr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u16 get_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) for (i = 0; i < viafb_load_reg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) reg_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) start_index = reg[i].start_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) end_index = reg[i].end_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) cr_index = reg[i].io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) shift_next_reg = bit_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) for (j = start_index; j <= end_index; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /*if (bit_num==8) timing_value = timing_value >>8; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) reg_mask = reg_mask | (BIT0 << j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) get_bit = (timing_value & (BIT0 << bit_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) data | ((get_bit >> shift_next_reg) << start_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) bit_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (io_type == VIACR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Write Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for (i = 0; i < ItemNum; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) via_write_reg_mask(RegTable[i].port, RegTable[i].index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RegTable[i].value, RegTable[i].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int viafb_load_reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct io_register *reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) switch (set_iga) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case IGA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) viafb_load_reg_num = fetch_count_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) iga1_fetch_count_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) reg = fetch_count_reg.iga1_fetch_count_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case IGA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) viafb_load_reg_num = fetch_count_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) iga2_fetch_count_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) reg = fetch_count_reg.iga2_fetch_count_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int viafb_load_reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct io_register *reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (set_iga == IGA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) K800_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* If resolution > 1280x1024, expire length = 64, else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) expire length = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if ((hor_active > 1280) && (ver_active > 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) iga1_display_queue_expire_num = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) P880_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* If resolution > 1280x1024, expire length = 64, else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) expire length = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if ((hor_active > 1280) && (ver_active > 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) iga1_display_queue_expire_num = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) CN700_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* If resolution > 1280x1024, expire length = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else expire length = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if ((hor_active > 1280) && (ver_active > 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) iga1_display_queue_expire_num = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) CX700_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) K8M890_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) P4M890_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) P4M900_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) VX800_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) VX855_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) iga1_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) VX900_IGA1_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) iga1_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Set Display FIFO Depath Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Set Display FIFO Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) fifo_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) iga1_fifo_threshold_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) fifo_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) iga1_fifo_threshold_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* Set FIFO High Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) reg_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) fifo_high_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) iga1_fifo_high_threshold_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) fifo_high_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) iga1_fifo_high_threshold_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Set Display Queue Expire Num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) reg_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) (iga1_display_queue_expire_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) display_queue_expire_num_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) iga1_display_queue_expire_num_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) display_queue_expire_num_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) iga1_display_queue_expire_num_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) K800_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* If resolution > 1280x1024, expire length = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) else expire length = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if ((hor_active > 1280) && (ver_active > 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) iga2_display_queue_expire_num = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) P880_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* If resolution > 1280x1024, expire length = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) else expire length = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if ((hor_active > 1280) && (ver_active > 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) iga2_display_queue_expire_num = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) CN700_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* If resolution > 1280x1024, expire length = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) else expire length = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if ((hor_active > 1280) && (ver_active > 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) iga2_display_queue_expire_num = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) CX700_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) K8M890_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) P4M890_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) P4M900_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) VX800_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) VX855_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) iga2_fifo_high_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) VX900_IGA2_FIFO_HIGH_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) iga2_display_queue_expire_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Set Display FIFO Depath Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) reg_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Patch LCD in IGA2 case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) display_fifo_depth_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) iga2_fifo_depth_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) display_fifo_depth_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) iga2_fifo_depth_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) viafb_load_reg(reg_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) viafb_load_reg_num, reg, VIACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Set Display FIFO Depath Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) reg_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) display_fifo_depth_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) iga2_fifo_depth_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) display_fifo_depth_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) iga2_fifo_depth_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) viafb_load_reg(reg_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) viafb_load_reg_num, reg, VIACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* Set Display FIFO Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) fifo_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) iga2_fifo_threshold_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) fifo_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) iga2_fifo_threshold_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* Set FIFO High Threshold Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) reg_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) fifo_high_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) iga2_fifo_high_threshold_select_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) fifo_high_threshold_select_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) iga2_fifo_high_threshold_select_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* Set Display Queue Expire Num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) reg_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) (iga2_display_queue_expire_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) viafb_load_reg_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) display_queue_expire_num_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) iga2_display_queue_expire_num_reg.reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) display_queue_expire_num_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) iga2_display_queue_expire_num_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) int clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct via_pll_config cur, up, down, best = {0, 1, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) const u32 f0 = 14318180; /* X1 frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) int i, f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) cur.rshift = limits[i].rshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) cur.divisor = limits[i].divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) f = abs(get_pll_output_frequency(f0, cur) - clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) up = down = cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) up.multiplier++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) down.multiplier--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (abs(get_pll_output_frequency(f0, up) - clk) < f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) cur = up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) cur = down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (cur.multiplier < limits[i].multiplier_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) cur.multiplier = limits[i].multiplier_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) else if (cur.multiplier > limits[i].multiplier_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) cur.multiplier = limits[i].multiplier_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) f = abs(get_pll_output_frequency(f0, cur) - clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (f < abs(get_pll_output_frequency(f0, best) - clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) best = cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static struct via_pll_config get_best_pll_config(int clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct via_pll_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case UNICHROME_CLE266:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) case UNICHROME_K400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) config = get_pll_config(cle266_pll_limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ARRAY_SIZE(cle266_pll_limits), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case UNICHROME_K800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case UNICHROME_PM800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) case UNICHROME_CN700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) config = get_pll_config(k800_pll_limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ARRAY_SIZE(k800_pll_limits), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case UNICHROME_CX700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case UNICHROME_CN750:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) case UNICHROME_VX800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) config = get_pll_config(cx700_pll_limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ARRAY_SIZE(cx700_pll_limits), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) case UNICHROME_VX855:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case UNICHROME_VX900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) config = get_pll_config(vx855_pll_limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ARRAY_SIZE(vx855_pll_limits), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Set VCLK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) void viafb_set_vclock(u32 clk, int set_iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct via_pll_config config = get_best_pll_config(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (set_iga == IGA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) clock.set_primary_pll(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (set_iga == IGA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) clock.set_secondary_pll(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* Fire! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct via_display_timing var_to_timing(const struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) u16 cxres, u16 cyres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct via_display_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) u16 dx = (var->xres - cxres) / 2, dy = (var->yres - cyres) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) timing.hor_addr = cxres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) timing.hor_sync_start = timing.hor_addr + var->right_margin + dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) timing.hor_sync_end = timing.hor_sync_start + var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) timing.hor_total = timing.hor_sync_end + var->left_margin + dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) timing.hor_blank_start = timing.hor_addr + dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) timing.hor_blank_end = timing.hor_total - dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) timing.ver_addr = cyres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) timing.ver_sync_end = timing.ver_sync_start + var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) timing.ver_total = timing.ver_sync_end + var->upper_margin + dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) timing.ver_blank_start = timing.ver_addr + dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) timing.ver_blank_end = timing.ver_total - dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u16 cxres, u16 cyres, int iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct via_display_timing crt_reg = var_to_timing(var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) cxres ? cxres : var->xres, cyres ? cyres : var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (iga == IGA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) via_set_primary_timing(&crt_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) else if (iga == IGA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) via_set_secondary_timing(&crt_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) viafb_load_fetch_count_reg(var->xres, var->bits_per_pixel / 8, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) && viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) viafb_load_FIFO_reg(iga, var->xres, var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) viafb_set_vclock(PICOS2KHZ(var->pixclock) * 1000, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) void viafb_init_chip_info(int chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) via_clock_init(&clock, chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) init_gfx_chip_info(chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) init_tmds_chip_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) init_lvds_chip_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*Set IGA path for each device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) viafb_set_iga_path();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) viaparinfo->lvds_setting_info2->display_method =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) viaparinfo->lvds_setting_info->display_method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) viaparinfo->lvds_setting_info2->lcd_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) viaparinfo->lvds_setting_info->lcd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) void viafb_update_device_setting(int hres, int vres, int bpp, int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (flag == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) viaparinfo->tmds_setting_info->h_active = hres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) viaparinfo->tmds_setting_info->v_active = vres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) viaparinfo->tmds_setting_info->h_active = hres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) viaparinfo->tmds_setting_info->v_active = vres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static void init_gfx_chip_info(int chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) viaparinfo->chip_info->gfx_chip_name = chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* Check revision of CLE266 Chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* CR4F only define in CLE266.CX chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) tmp = viafb_read_reg(VIACR, CR4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) viafb_write_reg(CR4F, VIACR, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (viafb_read_reg(VIACR, CR4F) != 0x55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) viaparinfo->chip_info->gfx_chip_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) CLE266_REVISION_AX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) viaparinfo->chip_info->gfx_chip_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) CLE266_REVISION_CX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* restore orignal CR4F value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) viafb_write_reg(CR4F, VIACR, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) tmp = viafb_read_reg(VIASR, SR43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (tmp & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) viaparinfo->chip_info->gfx_chip_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) CX700_REVISION_700M2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) } else if (tmp & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) viaparinfo->chip_info->gfx_chip_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) CX700_REVISION_700M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) viaparinfo->chip_info->gfx_chip_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) CX700_REVISION_700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Determine which 2D engine we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) case UNICHROME_VX800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) case UNICHROME_VX855:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) case UNICHROME_VX900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static void init_tmds_chip_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) viafb_tmds_trasmitter_identify();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) output_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) case UNICHROME_CX700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* we should check support by hardware layout.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if ((viafb_display_hardware_layout ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) HW_LAYOUT_DVI_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) || (viafb_display_hardware_layout ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) HW_LAYOUT_LCD_DVI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) viaparinfo->chip_info->tmds_chip_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) output_interface = INTERFACE_TMDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) viaparinfo->chip_info->tmds_chip_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) output_interface =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) INTERFACE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* TMDS on PCIE, we set DFPLOW as default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) viaparinfo->chip_info->tmds_chip_info.output_interface =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) INTERFACE_DFP_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* set DVP1 default for DVI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) viaparinfo->chip_info->tmds_chip_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .output_interface = INTERFACE_DVP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) &viaparinfo->shared->tmds_setting_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static void init_lvds_chip_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) viafb_lvds_trasmitter_identify();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) viafb_init_lcd_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) viaparinfo->lvds_setting_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) viafb_init_lvds_output_interface(&viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) lvds_chip_info2, viaparinfo->lvds_setting_info2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /*If CX700,two singel LCD, we need to reassign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) LCD interface to different LVDS port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) lvds_chip_name) && (INTEGRATED_LVDS ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) lvds_chip_info2.lvds_chip_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) viaparinfo->chip_info->lvds_chip_info.output_interface =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) INTERFACE_LVDS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) viaparinfo->chip_info->lvds_chip_info2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) output_interface =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) INTERFACE_LVDS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) viaparinfo->chip_info->lvds_chip_info.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) viaparinfo->chip_info->lvds_chip_info.output_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) void viafb_init_dac(int set_iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (set_iga == IGA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* access Primary Display's LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) /* turn off LCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) for (i = 0; i < 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) write_dac_reg(i, palLUT_table[i].red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) palLUT_table[i].green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) palLUT_table[i].blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* turn on LCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) tmp = viafb_read_reg(VIACR, CR6A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* access Secondary Display's LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) for (i = 0; i < 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) write_dac_reg(i, palLUT_table[i].red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) palLUT_table[i].green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) palLUT_table[i].blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* set IGA1 DAC for default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) viafb_write_reg(CR6A, VIACR, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static void device_screen_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* turn off CRT screen (IGA1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static void device_screen_on(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* turn on CRT screen (IGA1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static void set_display_channel(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /*If viafb_LCD2_ON, on cx700, internal lvds's information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) is keeped on lvds_setting_info2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (viafb_LCD2_ON &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* For dual channel LCD: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Set to Dual LVDS channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else if (viafb_LCD_ON && viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* For LCD+DFP: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /* Set to LVDS1 + TMDS channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) } else if (viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* Set to single TMDS channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) } else if (viafb_LCD_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* For dual channel LCD: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* Set to Dual LVDS channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /* Set to LVDS0 + LVDS1 channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static u8 get_sync(struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) u8 polarity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) polarity |= VIA_HSYNC_NEGATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) polarity |= VIA_VSYNC_NEGATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static void hw_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) inb(VIAStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) outb(0x00, VIAAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* Write Common Setting for Video Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) viafb_write_regx(common_vga, ARRAY_SIZE(common_vga));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) case UNICHROME_CLE266:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) case UNICHROME_K400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case UNICHROME_K800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) case UNICHROME_PM800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) case UNICHROME_CN700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) case UNICHROME_CX700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) case UNICHROME_VX800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) case UNICHROME_VX855:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) case UNICHROME_VX900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* magic required on VX900 for correct modesetting on IGA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) via_write_reg_mask(VIACR, 0x45, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /* probably this should go to the scaling code one day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* Fill VPIT Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* Write Misc Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) outb(VPIT.Misc, VIA_MISC_REG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* Write Sequencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) for (i = 1; i <= StdSR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) via_write_reg(VIASR, i, VPIT.SR[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* Write Graphic Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) for (i = 0; i < StdGR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) via_write_reg(VIAGR, i, VPIT.GR[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* Write Attribute Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) for (i = 0; i < StdAR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) inb(VIAStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) outb(i, VIAAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) outb(VPIT.AR[i], VIAAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) inb(VIAStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) outb(0x20, VIAAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) load_fix_bit_crtc_reg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) int viafb_setmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) int j, cxres = 0, cyres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 devices = viaparinfo->shared->iga1_devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) | viaparinfo->shared->iga2_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) u8 value, index, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct fb_var_screeninfo var2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) device_screen_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) device_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) via_set_state(devices, VIA_STATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) hw_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /* Update Patch Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) && viafbinfo->var.xres == 1024 && viafbinfo->var.yres == 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) for (j = 0; j < res_patch_table[0].table_length; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) index = res_patch_table[0].io_reg_table[j].index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) port = res_patch_table[0].io_reg_table[j].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) value = res_patch_table[0].io_reg_table[j].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) mask = res_patch_table[0].io_reg_table[j].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) viafb_write_reg_mask(index, port, value, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) via_set_primary_pitch(viafbinfo->fix.line_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) : viafbinfo->fix.line_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) via_set_primary_color_depth(viaparinfo->depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) : viaparinfo->depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) via_set_source(viaparinfo->shared->iga1_devices, IGA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) via_set_source(viaparinfo->shared->iga2_devices, IGA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (viaparinfo->shared->iga2_devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) enable_second_display_channel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) disable_second_display_channel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* Update Refresh Rate Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* Clear On Screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (viafb_dual_fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) var2 = viafbinfo1->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) } else if (viafb_SAMM_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) viafb_fill_var_timing_info(&var2, viafb_get_best_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) viafb_second_xres, viafb_second_yres, viafb_refresh1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) cxres = viafbinfo->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) cyres = viafbinfo->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) var2.bits_per_pixel = viafbinfo->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* CRT set mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (viafb_CRT_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (viaparinfo->shared->iga2_devices & VIA_CRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) && viafb_SAMM_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) viafb_fill_crtc_timing(&var2, cxres, cyres, IGA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) viafb_fill_crtc_timing(&viafbinfo->var, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) (viaparinfo->shared->iga1_devices & VIA_CRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ? IGA1 : IGA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) to 8 alignment (1368),there is several pixels (2 pixels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) on right side of screen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (viafbinfo->var.xres % 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) viafb_unlock_crt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) viafb_write_reg(CR02, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) viafb_read_reg(VIACR, CR02) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) viafb_lock_crt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (viafb_DVI_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (viaparinfo->shared->tmds_setting_info.iga_path == IGA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) && viafb_SAMM_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) viafb_dvi_set_mode(&var2, cxres, cyres, IGA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) viafb_dvi_set_mode(&viafbinfo->var, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) viaparinfo->tmds_setting_info->iga_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (viafb_LCD_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (viafb_SAMM_ON &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) viafb_lcd_set_mode(&var2, cxres, cyres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) viaparinfo->lvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) &viaparinfo->chip_info->lvds_chip_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* IGA1 doesn't have LCD scaling, so set it center. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) viaparinfo->lvds_setting_info->display_method =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) LCD_CENTERING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) viafb_lcd_set_mode(&viafbinfo->var, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) viaparinfo->lvds_setting_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) &viaparinfo->chip_info->lvds_chip_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (viafb_LCD2_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (viafb_SAMM_ON &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) viafb_lcd_set_mode(&var2, cxres, cyres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) viaparinfo->lvds_setting_info2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) &viaparinfo->chip_info->lvds_chip_info2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* IGA1 doesn't have LCD scaling, so set it center. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) viaparinfo->lvds_setting_info2->display_method =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) LCD_CENTERING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) viafb_lcd_set_mode(&viafbinfo->var, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) viaparinfo->lvds_setting_info2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) &viaparinfo->chip_info->lvds_chip_info2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) && (viafb_LCD_ON || viafb_DVI_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) set_display_channel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /* If set mode normally, save resolution information for hot-plug . */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (!viafb_hotplug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) viafb_hotplug_Xres = viafbinfo->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) viafb_hotplug_Yres = viafbinfo->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) viafb_hotplug_bpp = viafbinfo->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) viafb_hotplug_refresh = viafb_refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (viafb_DVI_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) viafb_DeviceStatus = DVI_Device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) viafb_DeviceStatus = CRT_Device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) device_on();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (!viafb_SAMM_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) via_set_sync_polarity(devices, get_sync(&viafbinfo->var));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) via_set_sync_polarity(viaparinfo->shared->iga1_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) get_sync(&viafbinfo->var));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) via_set_sync_polarity(viaparinfo->shared->iga2_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) get_sync(&var2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) clock.set_engine_pll_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #ifdef CONFIG_FB_VIA_X_COMPATIBILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) clock.set_primary_pll_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) clock.set_primary_clock_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) clock.set_secondary_pll_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) clock.set_secondary_clock_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (viaparinfo->shared->iga1_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) clock.set_primary_pll_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) clock.set_primary_clock_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) clock.set_primary_pll_state(VIA_STATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) clock.set_primary_clock_state(VIA_STATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (viaparinfo->shared->iga2_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) clock.set_secondary_pll_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) clock.set_secondary_clock_state(VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) clock.set_secondary_pll_state(VIA_STATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) clock.set_secondary_clock_state(VIA_STATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) via_set_state(devices, VIA_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) device_screen_on();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) int viafb_get_refresh(int hres, int vres, u32 long_refresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) const struct fb_videomode *best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) best = viafb_get_best_mode(hres, vres, long_refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (!best)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (abs(best->refresh - long_refresh) > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (hres == 1200 && vres == 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return 49; /* OLPC DCON only supports 50 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return best->refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static void device_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) viafb_dvi_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) viafb_lcd_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static void device_on(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (viafb_DVI_ON == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) viafb_dvi_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (viafb_LCD_ON == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) viafb_lcd_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static void enable_second_display_channel(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* to enable second display channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static void disable_second_display_channel(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* to disable second display channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) *p_gfx_dpa_setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) switch (output_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) case INTERFACE_DVP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* DVP0 Clock Polarity and Adjust: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) viafb_write_reg_mask(CR96, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) p_gfx_dpa_setting->DVP0, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) /* DVP0 Clock and Data Pads Driving: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) viafb_write_reg_mask(SR1E, VIASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) viafb_write_reg_mask(SR2A, VIASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) p_gfx_dpa_setting->DVP0ClockDri_S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) BIT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) viafb_write_reg_mask(SR1B, VIASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) viafb_write_reg_mask(SR2A, VIASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) case INTERFACE_DVP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* DVP1 Clock Polarity and Adjust: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) viafb_write_reg_mask(CR9B, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) p_gfx_dpa_setting->DVP1, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* DVP1 Clock and Data Pads Driving: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) viafb_write_reg_mask(SR65, VIASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) p_gfx_dpa_setting->DVP1Driving, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) case INTERFACE_DFP_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) viafb_write_reg_mask(CR97, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) p_gfx_dpa_setting->DFPHigh, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) case INTERFACE_DFP_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) viafb_write_reg_mask(CR99, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) p_gfx_dpa_setting->DFPLow, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) case INTERFACE_DFP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) viafb_write_reg_mask(CR97, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) p_gfx_dpa_setting->DFPHigh, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) viafb_write_reg_mask(CR99, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) p_gfx_dpa_setting->DFPLow, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) const struct fb_videomode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) var->pixclock = mode->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) var->xres = mode->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) var->yres = mode->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) var->left_margin = mode->left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) var->right_margin = mode->right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) var->hsync_len = mode->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) var->upper_margin = mode->upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) var->lower_margin = mode->lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) var->vsync_len = mode->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) var->sync = mode->sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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