Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/via-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/via_i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "global.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) static void tmds_register_write(int index, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) static int tmds_register_read(int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static void dvi_get_panel_size_from_DDCv1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	struct tmds_chip_information *tmds_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	struct tmds_setting_information *tmds_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static int viafb_dvi_query_EDID(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static inline bool check_tmds_chip(int device_id_subaddr, int device_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	return tmds_register_read(device_id_subaddr) == device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			 struct tmds_setting_information *tmds_setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	viafb_dvi_sense();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	if (viafb_dvi_query_EDID() == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) bool viafb_tmds_trasmitter_identify(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	/* Turn on ouputting pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	    /*=* DFP Low Pad on *=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		sr2a = viafb_read_reg(VIASR, SR2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		/* DFP Low Pad on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		sr2a = viafb_read_reg(VIASR, SR2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		/* DVP0 Pad on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		sr1e = viafb_read_reg(VIASR, SR1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	    /* DVP0/DVP1 Pad on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		sr1e = viafb_read_reg(VIASR, SR1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			BIT5 + BIT6 + BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	    /* SR3E[1]Multi-function selection:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	    0 = Emulate I2C and DDC bus by GPIO2/3/4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		sr3e = viafb_read_reg(VIASR, SR3E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* Check for VT1632: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		 * Currently only support 12bits,dual edge,add 24bits mode later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		tmds_register_write(0x08, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		DEBUG_MSG(KERN_INFO "\n %2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			  viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		DEBUG_MSG(KERN_INFO "\n %2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			  viaparinfo->chip_info->tmds_chip_info.i2c_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			tmds_register_write(0x08, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			DEBUG_MSG(KERN_INFO "\n %2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				  viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				  tmds_chip_info.tmds_chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			DEBUG_MSG(KERN_INFO "\n %2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				  viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				  tmds_chip_info.i2c_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	    ((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	     (viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		viafb_write_reg(SR2A, VIASR, sr2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		viafb_write_reg(SR2A, VIASR, sr2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		viafb_write_reg(SR1E, VIASR, sr1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		viafb_write_reg(SR1E, VIASR, sr1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		viafb_write_reg(SR3E, VIASR, sr3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	viaparinfo->chip_info->tmds_chip_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void tmds_register_write(int index, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			    viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			    index, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int tmds_register_read(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			   (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			   (u8) index, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			    (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			    (u8) index, buff, buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* DVI Set Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void viafb_dvi_set_mode(const struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u16 cxres, u16 cyres, int iga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct fb_var_screeninfo dvi_var = *var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	const struct fb_videomode *rb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int maxPixelClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	maxPixelClock = viaparinfo->shared->tmds_setting_info.max_pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (maxPixelClock && PICOS2KHZ(var->pixclock) / 1000 > maxPixelClock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		rb_mode = viafb_get_best_rb_mode(var->xres, var->yres, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (rb_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			viafb_fill_var_timing_info(&dvi_var, rb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	viafb_fill_crtc_timing(&dvi_var, cxres, cyres, iga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Sense DVI Connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int viafb_dvi_sense(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		RegCR93 = 0, RegCR9B = 0, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		/* DI1 Pad on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		RegSR1E = viafb_read_reg(VIASR, SR1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* CR6B[0]VCK Input Selection: 1 = External clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		RegCR6B = viafb_read_reg(VIACR, CR6B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		   [0] Software Control Power Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		RegCR91 = viafb_read_reg(VIACR, CR91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		viafb_write_reg(CR91, VIACR, 0x1D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		/* CR93[7] DI1 Data Source Selection: 1 = DSP2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		   CR93[5] DI1 Clock Source: 1 = internal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		   CR93[4] DI1 Clock Polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		   CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		RegCR93 = viafb_read_reg(VIACR, CR93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		viafb_write_reg(CR93, VIACR, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		/* DVP0/DVP1 Pad on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		RegSR1E = viafb_read_reg(VIASR, SR1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		/* SR3E[1]Multi-function selection:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		   0 = Emulate I2C and DDC bus by GPIO2/3/4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		RegSR3E = viafb_read_reg(VIASR, SR3E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		   [0] Software Control Power Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		RegCR91 = viafb_read_reg(VIACR, CR91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		viafb_write_reg(CR91, VIACR, 0x1D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		/*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		display.CR9B[2:0] DVP1 Clock Adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		RegCR9B = viafb_read_reg(VIACR, CR9B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		viafb_write_reg(CR9B, VIACR, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	data = (u8) tmds_register_read(0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (data & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (ret == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (viafb_dvi_query_EDID())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Restore status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	viafb_write_reg(SR1E, VIASR, RegSR1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	viafb_write_reg(CR91, VIACR, RegCR91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		viafb_write_reg(CR6B, VIACR, RegCR6B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		viafb_write_reg(CR93, VIACR, RegCR93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		viafb_write_reg(SR3E, VIASR, RegSR3E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		viafb_write_reg(CR9B, VIACR, RegCR9B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Query Flat Panel's EDID Table Version Through DVI Connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int viafb_dvi_query_EDID(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u8 data0, data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	int restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	data0 = (u8) tmds_register_read(0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	data1 = (u8) tmds_register_read(0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if ((data0 == 0) && (data1 == 0xFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			tmds_chip_info.tmds_chip_slave_addr = restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return EDID_VERSION_1;	/* Found EDID1 Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Get Panel Size Using EDID1 Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void dvi_get_panel_size_from_DDCv1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct tmds_chip_information *tmds_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct tmds_setting_information *tmds_setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int i, restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned char EDID_DATA[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	restore = tmds_chip->tmds_chip_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	tmds_chip->tmds_chip_slave_addr = 0xA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	for (i = 0x25; i < 0x6D; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		case 0x36:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		case 0x48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		case 0x5A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		case 0x6C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			tmds_register_read_bytes(i, EDID_DATA, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			if (!(EDID_DATA[0] || EDID_DATA[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				/* The first two byte must be zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				if (EDID_DATA[3] == 0xFD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					/* To get max pixel clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 					tmds_setting->max_pixel_clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 						EDID_DATA[9] * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		tmds_setting->max_pixel_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	tmds_chip->tmds_chip_slave_addr = restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* If Disable DVI, turn off pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void viafb_dvi_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		tmds_chip_info.output_interface == INTERFACE_TMDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		/* Turn off TMDS power. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		viafb_write_reg(CRD2, VIACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		viafb_read_reg(VIACR, CRD2) | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void dvi_patch_skew_dvp0(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	/* Reset data driving first: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				(viaparinfo->tmds_setting_info->v_active ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				1200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				viafb_write_reg_mask(CR96, VIACR, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 					       BIT0 + BIT1 + BIT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				viafb_write_reg_mask(CR96, VIACR, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					       BIT0 + BIT1 + BIT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			viafb_write_reg_mask(CR96, VIACR, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				       BIT0 + BIT1 + BIT2 + BIT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void dvi_patch_skew_dvp_low(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	switch (viaparinfo->chip_info->gfx_chip_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	case UNICHROME_K8M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	case UNICHROME_P4M900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			viafb_write_reg_mask(CR99, VIACR, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 				       BIT0 + BIT1 + BIT2 + BIT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	case UNICHROME_P4M890:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			viafb_write_reg_mask(CR99, VIACR, 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				       BIT0 + BIT1 + BIT2 + BIT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* If Enable DVI, turn off pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void viafb_dvi_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	case INTERFACE_DVP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		dvi_patch_skew_dvp0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			tmds_register_write(0x88, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			/*clear CR91[5] to direct on display period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			   in the secondary diplay path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	case INTERFACE_DVP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		/*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			tmds_register_write(0x88, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			/*clear CR91[5] to direct on display period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 			  in the secondary diplay path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		/*fix DVI cannot enable on EPIA-M board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		if (viafb_platform_epia_dvi == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			if (viafb_bus_width == 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 				if (viafb_device_lcd_dualedge == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 					data = 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 					data = 0x37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 				viafb_i2c_writebyte(viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 					tmds_chip_info.i2c_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 					viaparinfo->chip_info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 					tmds_chip_info.tmds_chip_slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 					0x08, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	case INTERFACE_DFP_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	case INTERFACE_DFP_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		dvi_patch_skew_dvp_low();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	case INTERFACE_TMDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		/* Turn on Display period in the panel path. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		/* Turn on TMDS power. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		/* Disable LCD Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }