^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __CHIP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __CHIP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "global.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Definition Graphic Chip Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /***************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_VIA_VENDOR_ID 0x1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Define VIA Graphic Chip Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNICHROME_CLE266 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNICHROME_CLE266_DID 0x3122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLE266_REVISION_AX 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLE266_REVISION_CX 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UNICHROME_K400 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UNICHROME_K400_DID 0x7205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UNICHROME_K800 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UNICHROME_K800_DID 0x3108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UNICHROME_PM800 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNICHROME_PM800_DID 0x3118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UNICHROME_CN700 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UNICHROME_CN700_DID 0x3344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UNICHROME_CX700 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UNICHROME_CX700_DID 0x3157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CX700_REVISION_700 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CX700_REVISION_700M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CX700_REVISION_700M2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UNICHROME_CN750 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UNICHROME_CN750_DID 0x3225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UNICHROME_K8M890 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UNICHROME_K8M890_DID 0x3230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UNICHROME_P4M890 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UNICHROME_P4M890_DID 0x3343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UNICHROME_P4M900 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UNICHROME_P4M900_DID 0x3371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UNICHROME_VX800 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UNICHROME_VX800_DID 0x1122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UNICHROME_VX855 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UNICHROME_VX855_DID 0x5122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UNICHROME_VX900 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UNICHROME_VX900_DID 0x7122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Definition TMDS Trasmitter Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Definition TMDS Trasmitter Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NON_TMDS_TRANSMITTER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VT1632_TMDS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define INTEGRATED_TMDS 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Definition TMDS Trasmitter I2C Slave Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VT1632_TMDS_I2C_ADDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /**************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Definition LVDS Trasmitter Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Definition LVDS Trasmitter Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NON_LVDS_TRANSMITTER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VT1631_LVDS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VT1636_LVDS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define INTEGRATED_LVDS 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Definition Digital Transmitter Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TX_DATA_12_BITS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TX_DATA_24_BITS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TX_DATA_DDR_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TX_DATA_SDR_MODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Definition LVDS Trasmitter I2C Slave Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VT1631_LVDS_I2C_ADDR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VT3271_LVDS_I2C_ADDR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VT1636_LVDS_I2C_ADDR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct tmds_chip_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int tmds_chip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int tmds_chip_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int output_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int i2c_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct lvds_chip_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int lvds_chip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int lvds_chip_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int output_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int i2c_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* The type of 2D engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum via_2d_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) VIA_2D_ENG_H2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) VIA_2D_ENG_H5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) VIA_2D_ENG_M1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct chip_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int gfx_chip_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int gfx_chip_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum via_2d_engine twod_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct tmds_chip_information tmds_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct lvds_chip_information lvds_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct lvds_chip_information lvds_chip_info2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct tmds_setting_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int iga_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int h_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int v_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int max_pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct lvds_setting_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int iga_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int lcd_panel_hres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int lcd_panel_vres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int display_method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int device_lcd_dualedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int LCDDithering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int lcd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 vclk; /*panel mode clock value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct GFX_DPA_SETTING {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ClkRangeIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 DVP0; /* CR96[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 DVP0DataDri_S1; /* SR2A[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 DVP0DataDri_S; /* SR1B[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 DVP0ClockDri_S1; /* SR2A[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 DVP0ClockDri_S; /* SR1E[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 DVP1; /* CR9B[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 DVP1Driving; /* SR65[3:0], Data and Clock driving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 DFPHigh; /* CR97[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 DFPLow; /* CR99[3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct VT1636_DPA_SETTING {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 CLK_SEL_ST1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 CLK_SEL_ST2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif /* __CHIP_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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