^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __ACCEL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __ACCEL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FB_ACCEL_VIA_UNICHROME 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* MMIO Base Address Definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MMIO_VGABASE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* HW Cursor Status Define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HW_Cursor_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HW_Cursor_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CURSOR_SIZE (8 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VQ_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VIA_MMIO_BLTBASE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VIA_MMIO_BLTSIZE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Defines for 2D registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VIA_REG_GECMD 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VIA_REG_GEMODE 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VIA_REG_SRCPOS 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VIA_REG_DSTPOS 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* width and height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIA_REG_DIMENSION 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIA_REG_PATADDR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIA_REG_FGCOLOR 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VIA_REG_BGCOLOR 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* top and left of clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIA_REG_CLIPTL 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* bottom and right of clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VIA_REG_CLIPBR 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIA_REG_OFFSET 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* color key control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VIA_REG_KEYCONTROL 0x02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VIA_REG_SRCBASE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VIA_REG_DSTBASE 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* pitch of src and dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VIA_REG_PITCH 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VIA_REG_MONOPAT0 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VIA_REG_MONOPAT1 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* from 0x100 to 0x1ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VIA_REG_COLORPAT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VIA_REG_GECMD_M1 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VIA_REG_GEMODE_M1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VIA_REG_DIMENSION_M1 0x00C /* width and height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VIA_REG_DSTPOS_M1 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VIA_REG_LINE_XY_M1 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VIA_REG_DSTBASE_M1 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VIA_REG_SRCPOS_M1 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VIA_REG_LINE_K1K2_M1 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VIA_REG_SRCBASE_M1 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VIA_REG_PATADDR_M1 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VIA_REG_MONOPAT0_M1 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VIA_REG_MONOPAT1_M1 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VIA_REG_OFFSET_M1 0x02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VIA_REG_LINE_ERROR_M1 0x02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VIA_REG_FGCOLOR_M1 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VIA_REG_BGCOLOR_M1 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VIA_REG_MONOPATFGC_M1 0x058 /* Add BG color of Pattern. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VIA_REG_MONOPATBGC_M1 0x05C /* Add FG color of Pattern. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* VIA_REG_PITCH(0x38): Pitch Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VIA_PITCH_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* defines for VIA HW cursor registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VIA_REG_CURSOR_MODE 0x2D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VIA_REG_CURSOR_POS 0x2D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VIA_REG_CURSOR_ORG 0x2D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VIA_REG_CURSOR_BG 0x2DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VIA_REG_CURSOR_FG 0x2E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* VIA_REG_GEMODE(0x04): GE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VIA_GEM_8bpp 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VIA_GEM_16bpp 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VIA_GEM_32bpp 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* VIA_REG_GECMD(0x00): 2D Engine Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VIA_GEC_NOOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VIA_GEC_BLT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VIA_GEC_LINE 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Rotate Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VIA_GEC_ROT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VIA_GEC_SRC_XY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VIA_GEC_SRC_LINEAR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VIA_GEC_DST_XY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VIA_GEC_DST_LINRAT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VIA_GEC_SRC_FB 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VIA_GEC_SRC_SYS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VIA_GEC_DST_FB 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VIA_GEC_DST_SYS 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* source is mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VIA_GEC_SRC_MONO 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* pattern is mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIA_GEC_PAT_MONO 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* mono src is opaque */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VIA_GEC_MSRC_OPAQUE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* mono src is transparent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIA_GEC_MSRC_TRANS 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* pattern is in frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VIA_GEC_PAT_FB 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* pattern is from reg setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIA_GEC_PAT_REG 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VIA_GEC_CLIP_DISABLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VIA_GEC_CLIP_ENABLE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VIA_GEC_FIXCOLOR_PAT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VIA_GEC_INCX 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VIA_GEC_DECY 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VIA_GEC_INCY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VIA_GEC_DECX 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* mono pattern is opaque */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VIA_GEC_MPAT_OPAQUE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* mono pattern is transparent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VIA_GEC_MPAT_TRANS 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VIA_GEC_MONO_UNPACK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VIA_GEC_MONO_PACK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VIA_GEC_MONO_DWORD 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VIA_GEC_MONO_WORD 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VIA_GEC_MONO_BYTE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VIA_GEC_LASTPIXEL_ON 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VIA_GEC_LASTPIXEL_OFF 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VIA_GEC_X_MAJOR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VIA_GEC_Y_MAJOR 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VIA_GEC_QUICK_START 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* defines for VIA 3D registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VIA_REG_STATUS 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VIA_REG_CR_TRANSET 0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIA_REG_CR_TRANSPACE 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VIA_REG_TRANSET 0x43C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VIA_REG_TRANSPACE 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* VIA_REG_STATUS(0x400): Engine Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Command Regulator is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VIA_CMD_RGTR_BUSY 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 2D Engine is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VIA_2D_ENG_BUSY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* 3D Engine is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VIA_3D_ENG_BUSY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Virtual Queue is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VIA_VR_QUEUE_BUSY 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* VIA_REG_STATUS(0x400): Engine Status for H5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VIA_CMD_RGTR_BUSY_M1 0x00000010 /* Command Regulator is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VIA_2D_ENG_BUSY_M1 0x00000002 /* 2D Engine is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define VIA_3D_ENG_BUSY_M1 0x00001FE1 /* 3D Engine is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define VIA_VR_QUEUE_BUSY_M1 0x00000004 /* Virtual Queue is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MAXLOOP 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VIA_BITBLT_COLOR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define VIA_BITBLT_MONO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define VIA_BITBLT_FILL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int viafb_setup_engine(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void viafb_reset_engine(struct viafb_par *viapar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void viafb_show_hw_cursor(struct fb_info *info, int Status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void viafb_wait_engine_idle(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif /* __ACCEL_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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