^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) Intel Corp. 2007.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * develop this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is part of the Vermilion Range fb driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef _VERMILION_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _VERMILION_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VML_DEVICE_GPU 0x5002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VML_DEVICE_VDC 0x5009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VML_VRAM_AREAS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VML_MAX_XRES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VML_MAX_YRES 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VML_MAX_XRES_VIRTUAL 1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Display controller registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Display controller 10-bit color representation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VML_R_MASK 0x3FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VML_R_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VML_G_MASK 0x000FFC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VML_G_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VML_B_MASK 0x000003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VML_B_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Graphics plane control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VML_DSPCCNTR 0x00072180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VML_GFX_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VML_GFX_GAMMABYPASS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VML_GFX_ARGB1555 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VML_GFX_RGB0888 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VML_GFX_ARGB8888 0x1C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VML_GFX_ALPHACONST 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VML_GFX_ALPHAMULT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VML_GFX_CONST_ALPHA 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Graphics plane start address. Pixel aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VML_DSPCADDR 0x00072184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Graphics plane stride register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VML_DSPCSTRIDE 0x00072188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Graphics plane position register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VML_DSPCPOS 0x0007218C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VML_POS_YMASK 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VML_POS_YSHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VML_POS_XMASK 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VML_POS_XSHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Graphics plane height and width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VML_DSPCSIZE 0x00072190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VML_SIZE_HMASK 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VML_SIZE_HSHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VML_SISE_WMASK 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VML_SIZE_WSHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VML_DSPCGAMLUT 0x00072200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Pixel video output configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VML_PVOCONFIG 0x00061140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VML_CONFIG_BASE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VML_CONFIG_PIXEL_SWAP 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VML_CONFIG_DE_INV 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VML_CONFIG_HREF_INV 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VML_CONFIG_VREF_INV 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VML_CONFIG_CLK_INV 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VML_CONFIG_CLK_DIV2 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VML_CONFIG_ESTRB_INV 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Pipe A Horizontal total register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VML_HTOTAL_A 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VML_HTOTAL_MASK 0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VML_HTOTAL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VML_HTOTAL_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VML_HACTIVE_MASK 0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VML_HACTIVE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VML_HACTIVE_VAL 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Pipe A Horizontal Blank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VML_HBLANK_A 0x00060004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VML_HBLANK_END_MASK 0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VML_HBLANK_END_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VML_HBLANK_END_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VML_HBLANK_START_MASK 0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VML_HBLANK_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VML_HBLANK_START_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Pipe A Horizontal Sync register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VML_HSYNC_A 0x00060008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VML_HSYNC_END_MASK 0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VML_HSYNC_END_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VML_HSYNC_END_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VML_HSYNC_START_MASK 0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VML_HSYNC_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VML_HSYNC_START_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Pipe A Vertical total register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VML_VTOTAL_A 0x0006000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VML_VTOTAL_MASK 0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VML_VTOTAL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VML_VTOTAL_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VML_VACTIVE_MASK 0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VML_VACTIVE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VML_VACTIVE_VAL 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Pipe A Vertical Blank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VML_VBLANK_A 0x00060010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VML_VBLANK_END_MASK 0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VML_VBLANK_END_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VML_VBLANK_END_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VML_VBLANK_START_MASK 0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VML_VBLANK_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VML_VBLANK_START_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Pipe A Vertical Sync register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VML_VSYNC_A 0x00060014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VML_VSYNC_END_MASK 0x1FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VML_VSYNC_END_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VML_VSYNC_END_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VML_VSYNC_START_MASK 0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VML_VSYNC_START_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VML_VSYNC_START_VAL 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Pipe A Source Image size (minus one - equal to active size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Programmable while pipe is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VML_PIPEASRC 0x0006001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VML_PIPEASRC_HMASK 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VML_PIPEASRC_HSHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VML_PIPEASRC_VMASK 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VML_PIPEASRC_VSHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Pipe A Border Color Pattern register (10 bit color) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VML_BCLRPAT_A 0x00060020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Pipe A Canvas Color register (10 bit color) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VML_CANVSCLR_A 0x00060024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Pipe A Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VML_PIPEACONF 0x00070008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VML_PIPE_BASE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VML_PIPE_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VML_PIPE_FORCE_BORDER 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VML_PIPE_PLANES_OFF 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Pipe A FIFO setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VML_DSPARB 0x00070030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VML_FIFO_DEFAULT 0x00001D9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* MDVO rcomp status & pads control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VML_RCOMPSTAT 0x00070048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VML_MDVO_VDC_I_RCOMP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VML_MDVO_POWERSAVE_OFF 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VML_MDVO_PAD_ENABLE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VML_MDVO_PULLDOWN_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct vml_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct pci_dev *vdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u64 vdc_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u64 vdc_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) char __iomem *vdc_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pci_dev *gpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u64 gpu_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u64 gpu_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) char __iomem *gpu_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) atomic_t refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct vram_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long logical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct vml_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct fb_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct vml_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct list_head head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct vram_area vram[VML_VRAM_AREAS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u64 vram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u64 vram_contig_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 num_areas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void __iomem *vram_logical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 bytes_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) atomic_t vmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int cur_blank_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int pipe_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct vml_sys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Save / Restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int (*save) (struct vml_sys * sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int (*restore) (struct vml_sys * sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * PLL programming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int (*set_clock) (struct vml_sys * sys, int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int (*nearest_clock) (const struct vml_sys * sys, int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) extern int vmlfb_register_subsys(struct vml_sys *sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) extern void vmlfb_unregister_subsys(struct vml_sys *sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VML_READ32(_par, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (ioread32((_par)->vdc_mem + (_offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VML_WRITE32(_par, _offset, _value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) iowrite32(_value, (_par)->vdc_mem + (_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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