^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * valkyriefb.h: Constants of all sorts for valkyriefb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Created 8 August 1998 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Martin Costabel <costabel@wanadoo.fr> and Kevin Schoedel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Vmode-switching changes and vmode 15/17 modifications created 29 August
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1998 by Barry K. Nathan <barryn@pobox.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * vmode 10 changed by Steven Borley <sjb@salix.demon.co.uk>, 14 mai 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Ported to 68k Macintosh by David Huggins-Daines <dhd@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Based directly on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * controlfb.h: Constants of all sorts for controlfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright (C) 1998 Daniel Jacobowitz <dan@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * pmc-valkyrie.h: Console support for PowerMac "control" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (C) 1997 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * pmc-valkyrie.c: Console support for PowerMac "control" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Copyright (C) 1997 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * and indirectly from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * pmc-control.h: Console support for PowerMac "control" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Copyright (C) 1997 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * pmc-control.c: Console support for PowerMac "control" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * platinumfb.c: Console support for PowerMac "platinum" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Copyright (C) 1998 Jon Howell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifdef CONFIG_MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Valkyrie registers are word-aligned on m68k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VALKYRIE_REG_PADSIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VALKYRIE_REG_PADSIZE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Structure of the registers for the Valkyrie colormap registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct cmap_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) char pad1[VALKYRIE_REG_PADSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned char lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Structure of the registers for the "valkyrie" display adaptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct vpreg { /* padded register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned char r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) char pad[VALKYRIE_REG_PADSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct valkyrie_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct vpreg mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct vpreg depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct vpreg status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct vpreg reg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct vpreg intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct vpreg reg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct vpreg intr_enb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct vpreg msense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Register initialization tables for the valkyrie display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Dot clock rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct valkyrie_regvals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned char mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned char clock_params[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int pitch[2]; /* bytes/line, indexed by color_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int hres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int vres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifndef CONFIG_MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Register values for 1024x768, 75Hz mode (17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* I'm not sure which mode this is (16 or 17), so I'm defining it as 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * since the equivalent mode in controlfb (which I adapted this from) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * also 17. Just because MacOS can't do this on Valkyrie doesn't mean we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * can't! :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * I was going to use 12, 31, 3, which I found by myself, but instead I'm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * using 11, 28, 3 like controlfb, for consistency's sake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct valkyrie_regvals valkyrie_reg_init_17 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 1024, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 1024, 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Register values for 1024x768, 72Hz mode (15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * that didn't match MacOS in the same video mode on this chip, and it also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * caused the 15" Apple Studio Display to not work in this mode. While this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * mode still doesn't match MacOS exactly (as far as I can tell), it's a lot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * closer now, and it works with the Apple Studio Display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Yes, even though MacOS calls it "72Hz", in reality it's about 70Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct valkyrie_regvals valkyrie_reg_init_15 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* I interpolated the V=69.71 from the vmode 14 and old 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * numbers. Is this result correct?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 1024, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 1024, 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Register values for 1024x768, 60Hz mode (14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct valkyrie_regvals valkyrie_reg_init_14 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 1024, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 1024, 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif /* !defined CONFIG_MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Register values for 832x624, 75Hz mode (13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct valkyrie_regvals valkyrie_reg_init_13 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 832, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 832, 624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Register values for 800x600, 72Hz mode (11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct valkyrie_regvals valkyrie_reg_init_11 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 800, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 800, 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Register values for 800x600, 60Hz mode (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct valkyrie_regvals valkyrie_reg_init_10 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 800, 1600 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 800, 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Register values for 640x480, 67Hz mode (6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct valkyrie_regvals valkyrie_reg_init_6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 640, 1280 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 640, 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Register values for 640x480, 60Hz mode (5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct valkyrie_regvals valkyrie_reg_init_5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 23, 37, 2 }, /* pixel clock = 25.14MHz for V=59.85Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 640, 1280 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 640, 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct valkyrie_regvals *valkyrie_reg_init[VMODE_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &valkyrie_reg_init_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &valkyrie_reg_init_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &valkyrie_reg_init_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &valkyrie_reg_init_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &valkyrie_reg_init_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifndef CONFIG_MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &valkyrie_reg_init_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &valkyrie_reg_init_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &valkyrie_reg_init_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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