^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Frame buffer driver for Trident TGUI, Blade and Image series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * CREDITS:(in order of appearance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * much inspired by the XFree86 4.x Trident driver sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * by Alan Hourihane the FreeVGA project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * code, suggestions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * timing value tweaking so it looks good on every monitor in every mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <video/trident.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct tridentfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *io_virt; /* iospace virtual memory address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 pseudo_pal[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int flatpanel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void (*init_accel) (struct tridentfb_par *, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void (*wait_engine) (struct tridentfb_par *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void (*fill_rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void (*copy_rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void (*image_blit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (struct tridentfb_par *par, const char*,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32, u32, u32, u32, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned char eng_oper; /* engine operation... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool ddc_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct i2c_adapter ddc_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct i2c_algo_bit_data ddc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct fb_fix_screeninfo tridentfb_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .id = "Trident",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .ypanstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .visual = FB_VISUAL_PSEUDOCOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .accel = FB_ACCEL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* defaults which are normally overriden by user values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static char *mode_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int bpp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int noaccel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int stretch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int crt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int memdiff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int nativex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) module_param(mode_option, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) module_param_named(mode, mode_option, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) module_param(bpp, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) module_param(center, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_param(stretch, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) module_param(noaccel, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) module_param(memsize, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param(memdiff, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) module_param(nativex, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) module_param(fp, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param(crt, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(crt, "Define if CRT is connected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline int is_oldclock(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return (id == TGUI9440) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (id == TGUI9660) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (id == CYBER9320);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline int is_oldprotect(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return is_oldclock(id) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (id == PROVIDIA9685) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (id == CYBER9382) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (id == CYBER9385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline int is_blade(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return (id == BLADE3D) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (id == CYBERBLADEE4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (id == CYBERBLADEi7) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (id == CYBERBLADEi7D) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (id == CYBERBLADEi1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (id == CYBERBLADEi1D) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (id == CYBERBLADEAi1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (id == CYBERBLADEAi1D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline int is_xp(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return (id == CYBERBLADEXPAi1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (id == CYBERBLADEXPm8) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (id == CYBERBLADEXPm16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline int is3Dchip(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return is_blade(id) || is_xp(id) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (id == CYBER9397) || (id == CYBER9397DVD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (id == CYBER9520) || (id == CYBER9525DVD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (id == IMAGE975) || (id == IMAGE985);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline int iscyber(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case CYBER9388:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case CYBER9382:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case CYBER9385:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case CYBER9397:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case CYBER9397DVD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case CYBER9520:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case CYBER9525DVD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case CYBERBLADEE4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case CYBERBLADEi7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case CYBERBLADEi1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case CYBERBLADEi1D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case CYBERBLADEAi1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case CYBERBLADEAi1D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case CYBERBLADEXPAi1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case CYBER9320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case CYBERBLADEi7: /* VIA MPV4 integrated version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* case CYBERBLDAEXPm8: Strange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* case CYBERBLDAEXPm16: Strange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) fb_writeb(val, p->io_virt + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return fb_readb(p->io_virt + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fb_writel(v, par->io_virt + r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline u32 readmmr(struct tridentfb_par *par, u16 r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return fb_readl(par->io_virt + r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DDC_SDA_TGUI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DDC_SCL_TGUI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DDC_SCL_DRIVE_TGUI BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DDC_SDA_DRIVE_TGUI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DDC_MASK_TGUI (DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void tridentfb_ddc_setscl_tgui(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) vga_mm_wcrt(par->io_virt, I2C, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void tridentfb_ddc_setsda_tgui(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) vga_mm_wcrt(par->io_virt, I2C, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int tridentfb_ddc_getsda_tgui(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DDC_SDA_IN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DDC_SCL_OUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DDC_SDA_OUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DDC_SCL_IN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DDC_MASK (DDC_SCL_OUT | DDC_SDA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void tridentfb_ddc_setscl(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) reg |= DDC_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg &= ~DDC_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) vga_mm_wcrt(par->io_virt, I2C, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void tridentfb_ddc_setsda(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg |= DDC_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg &= ~DDC_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) vga_mm_wcrt(par->io_virt, I2C, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int tridentfb_ddc_getscl(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int tridentfb_ddc_getsda(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct tridentfb_par *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int tridentfb_setup_ddc_bus(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) strlcpy(par->ddc_adapter.name, info->fix.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sizeof(par->ddc_adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) par->ddc_adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) par->ddc_adapter.class = I2C_CLASS_DDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) par->ddc_adapter.algo_data = &par->ddc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) par->ddc_adapter.dev.parent = info->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* no getscl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) par->ddc_algo.setsda = tridentfb_ddc_setsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) par->ddc_algo.setscl = tridentfb_ddc_setscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) par->ddc_algo.getsda = tridentfb_ddc_getsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) par->ddc_algo.getscl = tridentfb_ddc_getscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) par->ddc_algo.udelay = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) par->ddc_algo.timeout = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) par->ddc_algo.data = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) i2c_set_adapdata(&par->ddc_adapter, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return i2c_bit_add_bus(&par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Blade specific acceleration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define point(x, y) ((y) << 16 | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int v1 = (pitch >> 3) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int tmp = bpp == 24 ? 2 : (bpp >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int v2 = v1 | (tmp << 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writemmr(par, 0x21C0, v2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writemmr(par, 0x21C4, v2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writemmr(par, 0x21B8, v2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writemmr(par, 0x21BC, v2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writemmr(par, 0x21D0, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) writemmr(par, 0x21D4, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writemmr(par, 0x21C8, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writemmr(par, 0x21CC, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writemmr(par, 0x216C, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void blade_wait_engine(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while (readmmr(par, STATUS) & 0xFA800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void blade_fill_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writemmr(par, COLOR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writemmr(par, ROP, rop ? ROP_X : ROP_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) writemmr(par, DST1, point(x, y));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writemmr(par, DST2, point(x + w - 1, y + h - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void blade_image_blit(struct tridentfb_par *par, const char *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned size = ((w + 31) >> 5) * h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writemmr(par, COLOR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writemmr(par, BGCOLOR, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writemmr(par, CMD, 0xa0000000 | 3 << 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writemmr(par, DST1, point(x, y));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writemmr(par, DST2, point(x + w - 1, y + h - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) iowrite32_rep(par->io_virt + 0x10000, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void blade_copy_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int direction = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 s1 = point(x1, y1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 s2 = point(x1 + w - 1, y1 + h - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 d1 = point(x2, y2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 d2 = point(x2 + w - 1, y2 + h - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writemmr(par, ROP, ROP_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writemmr(par, SRC1, direction ? s2 : s1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writemmr(par, SRC2, direction ? s1 : s2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writemmr(par, DST1, direction ? d2 : d1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writemmr(par, DST2, direction ? d1 : d2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * BladeXP specific acceleration functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) switch (pitch << (bpp >> 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case 8192:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) x |= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case 1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) x |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case 2048:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) x |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case 4096:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) x |= 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) t_outb(par, x, 0x2125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) par->eng_oper = x | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writemmr(par, 0x2154, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writemmr(par, 0x2150, v1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) t_outb(par, 3, 0x2126);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void xp_wait_engine(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) while (t_inb(par, STATUS) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (count == 10000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) count = 9990000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (timeout == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Reset engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) t_outb(par, 0x00, STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void xp_fill_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writemmr(par, 0x2127, ROP_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writemmr(par, 0x2158, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writemmr(par, DRAWFL, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writemmr(par, OLDDIM, point(h, w));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) writemmr(par, OLDDST, point(y, x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) t_outb(par, 0x01, OLDCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) t_outb(par, par->eng_oper, 0x2125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void xp_copy_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int direction = 0x0004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((x1 < x2) && (y1 == y2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) direction |= 0x0200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) x1_tmp = x1 + w - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) x2_tmp = x2 + w - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) x1_tmp = x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) x2_tmp = x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (y1 < y2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) direction |= 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) y1_tmp = y1 + h - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) y2_tmp = y2 + h - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) y1_tmp = y1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) y2_tmp = y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writemmr(par, DRAWFL, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) t_outb(par, ROP_S, 0x2127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writemmr(par, OLDDIM, point(h, w));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) t_outb(par, 0x01, OLDCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Image specific acceleration functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int tmp = bpp == 24 ? 2: (bpp >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) writemmr(par, 0x2120, 0xF0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) writemmr(par, 0x2120, 0x40000000 | tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writemmr(par, 0x2120, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) writemmr(par, 0x2144, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) writemmr(par, 0x2148, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writemmr(par, 0x2150, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writemmr(par, 0x2154, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writemmr(par, 0x216C, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writemmr(par, 0x2170, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) writemmr(par, 0x217C, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writemmr(par, 0x2120, 0x10000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) writemmr(par, 0x2130, (2047 << 16) | 2047);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void image_wait_engine(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) while (readmmr(par, 0x2164) & 0xF0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void image_fill_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writemmr(par, 0x2120, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) writemmr(par, 0x2120, 0x90000000 | ROP_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writemmr(par, 0x2144, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writemmr(par, DST1, point(x, y));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) writemmr(par, DST2, point(x + w - 1, y + h - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void image_copy_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int direction = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 s1 = point(x1, y1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 s2 = point(x1 + w - 1, y1 + h - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 d1 = point(x2, y2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 d2 = point(x2 + w - 1, y2 + h - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writemmr(par, 0x2120, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writemmr(par, 0x2120, 0x90000000 | ROP_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) writemmr(par, SRC1, direction ? s2 : s1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writemmr(par, SRC2, direction ? s1 : s2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) writemmr(par, DST1, direction ? d2 : d1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) writemmr(par, DST2, direction ? d1 : d2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writemmr(par, 0x2124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * TGUI 9440/96XX acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* disable clipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writemmr(par, 0x2148, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) writemmr(par, 0x214C, point(4095, 2047));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) switch ((pitch * bpp) / 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case 8192:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) x |= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case 1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) x |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 2048:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) x |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case 4096:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) x |= 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) fb_writew(x, par->io_virt + 0x2122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void tgui_fill_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) t_outb(par, ROP_P, 0x2127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writemmr(par, OLDCLR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) writemmr(par, DRAWFL, 0x4020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) writemmr(par, OLDDIM, point(w - 1, h - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) writemmr(par, OLDDST, point(x, y));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) t_outb(par, 1, OLDCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void tgui_copy_rect(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if ((x1 < x2) && (y1 == y2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) flags |= 0x0200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) x1_tmp = x1 + w - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) x2_tmp = x2 + w - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) x1_tmp = x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) x2_tmp = x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (y1 < y2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) flags |= 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) y1_tmp = y1 + h - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) y2_tmp = y2 + h - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) y1_tmp = y1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) y2_tmp = y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) writemmr(par, DRAWFL, 0x4 | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) t_outb(par, ROP_S, 0x2127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writemmr(par, OLDDIM, point(w - 1, h - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) t_outb(par, 1, OLDCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Accel functions called by the upper layers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static void tridentfb_fillrect(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) const struct fb_fillrect *fr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (info->flags & FBINFO_HWACCEL_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cfb_fillrect(info, fr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (info->var.bits_per_pixel == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) col = fr->color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) col |= col << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) col |= col << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) col = ((u32 *)(info->pseudo_palette))[fr->color];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) par->wait_engine(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) par->fill_rect(par, fr->dx, fr->dy, fr->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fr->height, col, fr->rop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void tridentfb_imageblit(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) const struct fb_image *img)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int col, bgcol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) cfb_imageblit(info, img);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (info->var.bits_per_pixel == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) col = img->fg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) col |= col << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) col |= col << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) bgcol = img->bg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bgcol |= bgcol << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) bgcol |= bgcol << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) col = ((u32 *)(info->pseudo_palette))[img->fg_color];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) par->wait_engine(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (par->image_blit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) par->image_blit(par, img->data, img->dx, img->dy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) img->width, img->height, col, bgcol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cfb_imageblit(info, img);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void tridentfb_copyarea(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) const struct fb_copyarea *ca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (info->flags & FBINFO_HWACCEL_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) cfb_copyarea(info, ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) par->wait_engine(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ca->width, ca->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int tridentfb_sync(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!(info->flags & FBINFO_HWACCEL_DISABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) par->wait_engine(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * Hardware access functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return vga_mm_rcrt(par->io_virt, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static inline void write3X4(struct tridentfb_par *par, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) vga_mm_wcrt(par->io_virt, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static inline unsigned char read3CE(struct tridentfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return vga_mm_rgfx(par->io_virt, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static inline void writeAttr(struct tridentfb_par *par, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) vga_mm_wattr(par->io_virt, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static inline void write3CE(struct tridentfb_par *par, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) vga_mm_wgfx(par->io_virt, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void enable_mmio(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Goto New Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) vga_io_rseq(0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Unprotect registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) vga_io_wseq(NewMode1, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (!is_oldprotect(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) vga_io_wseq(Protection, 0x92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Enable MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) outb(PCIReg, 0x3D4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) outb(inb(0x3D5) | 0x01, 0x3D5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void disable_mmio(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Goto New Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) vga_mm_rseq(par->io_virt, 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Unprotect registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) vga_mm_wseq(par->io_virt, NewMode1, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!is_oldprotect(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) vga_mm_wseq(par->io_virt, Protection, 0x92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Disable MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) t_outb(par, PCIReg, 0x3D4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static inline void crtc_unlock(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) write3X4(par, VGA_CRTC_V_SYNC_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Return flat panel's maximum x resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int get_nativex(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int x, y, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (nativex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return nativex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) tmp = (read3CE(par, VertStretch) >> 4) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) switch (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) x = 1280; y = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) x = 1024; y = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) x = 800; y = 600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) x = 640; y = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) output("%dx%d flat panel found\n", x, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Set pitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static inline void set_lwidth(struct tridentfb_par *par, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* chips older than TGUI9660 have only 1 width bit in AddColReg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* touching the other one breaks I2C/DDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) write3X4(par, AddColReg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) write3X4(par, AddColReg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* For resolutions smaller than FP resolution stretch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void screen_stretch(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (par->chip_id != CYBERBLADEXPAi1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) write3CE(par, BiosReg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) write3CE(par, BiosReg, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* For resolutions smaller than FP resolution center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static inline void screen_center(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Address of first shown pixel in display memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void set_screen_start(struct tridentfb_par *par, int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tmp = read3X4(par, CRTCModuleTest) & 0xDF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) tmp = read3X4(par, CRTHiOrd) & 0xF8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Set dotclock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void set_vclk(struct tridentfb_par *par, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int m, n, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) unsigned long fi, d, di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned char best_m = 0, best_n = 0, best_k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned char hi, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) d = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (k = shift; k >= 0; k--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) for (m = 1; m < 32; m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) n = ((m + 2) << shift) - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) for (n = (n < 0 ? 0 : n); n < 122; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) fi = ((14318l * (n + 8)) / (m + 2)) >> k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) di = abs(fi - freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (di < d || (di == d && k == best_k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) d = di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) best_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) best_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) best_k = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (fi > freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (is_oldclock(par->chip_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) lo = best_n | (best_m << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hi = (best_m >> 1) | (best_k << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) lo = best_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) hi = best_m | (best_k << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (is3Dchip(par->chip_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) vga_mm_wseq(par->io_virt, ClockHigh, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) vga_mm_wseq(par->io_virt, ClockLow, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) t_outb(par, lo, 0x43C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) t_outb(par, hi, 0x43C9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) debug("VCLK = %X %X\n", hi, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Set number of lines for flat panels*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static void set_number_of_lines(struct tridentfb_par *par, int lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int tmp = read3CE(par, CyberEnhance) & 0x8F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (lines > 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) tmp |= 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) else if (lines > 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) tmp |= 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) else if (lines > 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) else if (lines > 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tmp |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) write3CE(par, CyberEnhance, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * If we see that FP is active we assume we have one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * Otherwise we have a CRT display. User can override.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int is_flatpanel(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (crt || !iscyber(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Try detecting the video memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static unsigned int get_memsize(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned char tmp, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) unsigned int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* If memory size provided by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) k = memsize * Kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) switch (par->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case CYBER9525DVD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) k = 2560 * Kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) tmp = read3X4(par, SPR) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) switch (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) k = 512 * Kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) k = 6 * Mb; /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) k = 1 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) k = 8 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case 0x06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) k = 10 * Mb; /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case 0x07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) k = 2 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) k = 12 * Mb; /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case 0x0A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) k = 14 * Mb; /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case 0x0C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) k = 16 * Mb; /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case 0x0E: /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) switch (tmp2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) k = 20 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) k = 24 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) k = 28 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) k = 32 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) k = 1 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case 0x0F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) k = 4 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) k = 1 * Mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) k -= memdiff * Kb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) output("framebuffer size = %d Kb\n", k / Kb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* See if we can handle the video mode described in var */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int tridentfb_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int bpp = var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int ramdac = 230000; /* 230MHz for most 3D chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) debug("enter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* check color depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (bpp == 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) bpp = var->bits_per_pixel = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (bpp != 8 && bpp != 16 && bpp != 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (par->chip_id == TGUI9440 && bpp == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* check whether resolution fits on panel and in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (par->flatpanel && nativex && var->xres > nativex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* various resolution checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) var->xres = (var->xres + 7) & ~0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (var->xres > var->xres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (var->yres > var->yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (var->xres_virtual > 4095 || var->yres > 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* prevent from position overflow for acceleration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (var->yres_virtual > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) line_length = var->xres_virtual * bpp / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!is3Dchip(par->chip_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) !(info->flags & FBINFO_HWACCEL_DISABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* acceleration requires line length to be power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (line_length <= 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) var->xres_virtual = 512 * 8 / bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) else if (line_length <= 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) var->xres_virtual = 1024 * 8 / bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) else if (line_length <= 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) var->xres_virtual = 2048 * 8 / bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) else if (line_length <= 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) var->xres_virtual = 4096 * 8 / bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) else if (line_length <= 8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) var->xres_virtual = 8192 * 8 / bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) line_length = var->xres_virtual * bpp / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* datasheet specifies how to set panning only up to 4 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) var->yres_virtual = ((4 << 20) / line_length) + var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (line_length * var->yres_virtual > info->fix.smem_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) switch (bpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) var->green = var->red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) var->blue = var->red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) var->red.offset = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (is_xp(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ramdac = 350000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) switch (par->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case TGUI9440:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ramdac = (bpp >= 16) ? 45000 : 90000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case CYBER9320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case TGUI9660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ramdac = 135000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case PROVIDIA9685:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) case CYBER9388:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case CYBER9382:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case CYBER9385:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ramdac = 170000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* The clock is doubled for 32 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (bpp == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ramdac /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (PICOS2KHZ(var->pixclock) > ramdac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) debug("exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Pan the display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int tridentfb_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) debug("enter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * info->var.bits_per_pixel / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) set_screen_start(par, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) debug("exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static inline void shadowmode_on(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static inline void shadowmode_off(struct tridentfb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Set the hardware to the requested video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int tridentfb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int bpp = var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) unsigned long vclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) debug("enter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) hdispend = var->xres / 8 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) hsyncstart = (var->xres + var->right_margin) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) htotal = (var->xres + var->left_margin + var->right_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) var->hsync_len) / 8 - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) hblankstart = hdispend + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) hblankend = htotal + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) vdispend = var->yres - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) vsyncstart = var->yres + var->lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) vsyncend = vsyncstart + var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) vtotal = var->upper_margin + vsyncend - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) vblankstart = vdispend + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) vblankend = vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (info->var.vmode & FB_VMODE_INTERLACED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) vtotal /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) vdispend /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) vsyncstart /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) vsyncend /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) vblankstart /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) vblankend /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) enable_mmio(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) crtc_unlock(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) write3CE(par, CyberControl, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) tmp = 0xEB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (var->sync & FB_SYNC_HOR_HIGH_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) tmp &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (var->sync & FB_SYNC_VERT_HIGH_ACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) tmp &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (par->flatpanel && var->xres < nativex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * on flat panels with native size larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * than requested resolution decide whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * we stretch or center
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) t_outb(par, tmp | 0xC0, VGA_MIS_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) shadowmode_on(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (center)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) screen_center(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) else if (stretch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) screen_stretch(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) t_outb(par, tmp, VGA_MIS_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) write3CE(par, CyberControl, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* vertical timing values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* horizontal timing values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) write3X4(par, VGA_CRTC_H_SYNC_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* higher bits of vertical timing values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) tmp = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (vtotal & 0x100) tmp |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (vdispend & 0x100) tmp |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (vsyncstart & 0x100) tmp |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (vblankstart & 0x100) tmp |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (vtotal & 0x200) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (vdispend & 0x200) tmp |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (vsyncstart & 0x200) tmp |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) write3X4(par, VGA_CRTC_OVERFLOW, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) tmp = read3X4(par, CRTHiOrd) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) tmp |= 0x08; /* line compare bit 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (vtotal & 0x400) tmp |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (vblankstart & 0x400) tmp |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (vsyncstart & 0x400) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (vdispend & 0x400) tmp |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) write3X4(par, CRTHiOrd, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) tmp = (htotal >> 8) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) tmp |= (hdispend >> 7) & 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) tmp |= (hsyncstart >> 5) & 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) tmp |= (hblankstart >> 4) & 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) write3X4(par, HorizOverflow, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) tmp = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (vblankstart & 0x200) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) write3X4(par, VGA_CRTC_PRESET_ROW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) write3X4(par, VGA_CRTC_MODE, 0xC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* enable access extended memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) write3X4(par, CRTCModuleTest, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) tmp = read3CE(par, MiscIntContReg) & ~0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (info->var.vmode & FB_VMODE_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) tmp |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) write3CE(par, MiscIntContReg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* enable GE for text acceleration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) write3X4(par, GraphEngReg, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) switch (bpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) tmp = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) tmp = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) tmp = 0x29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) tmp = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) write3X4(par, PixelBusReg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) tmp = read3X4(par, DRAMControl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (!is_oldprotect(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tmp |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (iscyber(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) tmp |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!is_xp(par->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) write3X4(par, Performance, read3X4(par, Performance) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* MMIO & PCI read and write burst enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) vga_mm_wseq(par->io_virt, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* enable 4 maps because needed in chain4 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) vga_mm_wseq(par->io_virt, 2, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) vga_mm_wseq(par->io_virt, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* convert from picoseconds to kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) vclk = PICOS2KHZ(info->var.pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) tmp = read3CE(par, MiscExtFunc) & 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) tmp |= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) vclk *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) set_vclk(par, vclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) write3CE(par, MiscExtFunc, tmp | 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) write3CE(par, 0x6, 0x05); /* graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) write3CE(par, 0x7, 0x0F); /* planes? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* graphics mode and support 256 color modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) writeAttr(par, 0x10, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) writeAttr(par, 0x12, 0x0F); /* planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) writeAttr(par, 0x13, 0); /* horizontal pel panning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* colors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) for (tmp = 0; tmp < 0x10; tmp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) writeAttr(par, tmp, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) switch (bpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) tmp = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) tmp = 0xD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) t_inb(par, VGA_PEL_IW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) t_inb(par, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) t_inb(par, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) t_inb(par, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) t_inb(par, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) t_outb(par, tmp, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) t_inb(par, VGA_PEL_IW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (par->flatpanel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) set_number_of_lines(par, info->var.yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) info->fix.line_length = info->var.xres_virtual * bpp / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) set_lwidth(par, info->fix.line_length / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (!(info->flags & FBINFO_HWACCEL_DISABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) par->init_accel(par, info->var.xres_virtual, bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) info->cmap.len = (bpp == 8) ? 256 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) debug("exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* Set one color register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) unsigned blue, unsigned transp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int bpp = info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (regno >= info->cmap.len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (bpp == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) t_outb(par, 0xFF, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) t_outb(par, regno, VGA_PEL_IW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) t_outb(par, red >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) t_outb(par, green >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) t_outb(par, blue >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } else if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (bpp == 16) { /* RGB 565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) u32 col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ((blue & 0xF800) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) col |= col << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ((u32 *)(info->pseudo_palette))[regno] = col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) } else if (bpp == 32) /* ARGB 8888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ((u32 *)info->pseudo_palette)[regno] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ((transp & 0xFF00) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ((red & 0xFF00) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ((green & 0xFF00)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ((blue & 0xFF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Try blanking the screen. For flat panels it does nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int tridentfb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) unsigned char PMCont, DPMSCont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) debug("enter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (par->flatpanel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PMCont = t_inb(par, 0x83C6) & 0xFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) DPMSCont = read3CE(par, PowerStatus) & 0xFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) switch (blank_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) case FB_BLANK_UNBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Screen: On, HSync: On, VSync: On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) case FB_BLANK_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Screen: Off, HSync: On, VSync: On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PMCont |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) DPMSCont |= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* Screen: Off, HSync: Off, VSync: On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PMCont |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) DPMSCont |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* Screen: Off, HSync: On, VSync: Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PMCont |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) DPMSCont |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* Screen: Off, HSync: Off, VSync: Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PMCont |= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) DPMSCont |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) write3CE(par, PowerStatus, DPMSCont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) t_outb(par, 4, 0x83C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) t_outb(par, PMCont, 0x83C6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) debug("exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* let fbcon do a softblank for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static const struct fb_ops tridentfb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .fb_setcolreg = tridentfb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .fb_pan_display = tridentfb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .fb_blank = tridentfb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .fb_check_var = tridentfb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .fb_set_par = tridentfb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .fb_fillrect = tridentfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .fb_copyarea = tridentfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .fb_imageblit = tridentfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .fb_sync = tridentfb_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static int trident_pci_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) unsigned char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct tridentfb_par *default_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) int chip3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) err = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) default_par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) chip_id = id->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* If PCI id is 0x9660 then further detect chip type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (chip_id == TGUI9660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) revision = vga_io_rseq(RevisionID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) switch (revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case 0x21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) chip_id = PROVIDIA9685;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) case 0x22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) case 0x23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) chip_id = CYBER9397;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) case 0x2A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) chip_id = CYBER9397DVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) case 0x30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) case 0x33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case 0x34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case 0x35:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) case 0x38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case 0x3A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) case 0xB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) chip_id = CYBER9385;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) case 0x40 ... 0x43:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) chip_id = CYBER9382;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) case 0x4A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) chip_id = CYBER9388;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) chip3D = is3Dchip(chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (is_xp(chip_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) default_par->init_accel = xp_init_accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) default_par->wait_engine = xp_wait_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) default_par->fill_rect = xp_fill_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) default_par->copy_rect = xp_copy_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) } else if (is_blade(chip_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) default_par->init_accel = blade_init_accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) default_par->wait_engine = blade_wait_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) default_par->fill_rect = blade_fill_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) default_par->copy_rect = blade_copy_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) default_par->image_blit = blade_image_blit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) } else if (chip3D) { /* 3DImage family left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) default_par->init_accel = image_init_accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) default_par->wait_engine = image_wait_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) default_par->fill_rect = image_fill_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) default_par->copy_rect = image_copy_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) } else { /* TGUI 9440/96XX family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) default_par->init_accel = tgui_init_accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) default_par->wait_engine = xp_wait_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) default_par->fill_rect = tgui_fill_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) default_par->copy_rect = tgui_copy_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) default_par->chip_id = chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* setup MMIO region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (!request_mem_region(tridentfb_fix.mmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) tridentfb_fix.mmio_len, "tridentfb")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) debug("request_region failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) default_par->io_virt = ioremap(tridentfb_fix.mmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) tridentfb_fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (!default_par->io_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) debug("ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) goto out_unmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) enable_mmio(default_par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* setup framebuffer memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) tridentfb_fix.smem_start = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) tridentfb_fix.smem_len = get_memsize(default_par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (!request_mem_region(tridentfb_fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) tridentfb_fix.smem_len, "tridentfb")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) debug("request_mem_region failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) disable_mmio(info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) goto out_unmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) info->screen_base = ioremap(tridentfb_fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) tridentfb_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) debug("ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) default_par->flatpanel = is_flatpanel(default_par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (default_par->flatpanel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) nativex = get_nativex(default_par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) info->fix = tridentfb_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) info->fbops = &tridentfb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) info->pseudo_palette = default_par->pseudo_pal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (!noaccel && default_par->init_accel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) info->flags &= ~FBINFO_HWACCEL_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) info->flags |= FBINFO_HWACCEL_COPYAREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) info->flags |= FBINFO_HWACCEL_FILLRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) info->flags |= FBINFO_HWACCEL_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (is_blade(chip_id) && chip_id != BLADE3D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) info->flags |= FBINFO_READS_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!info->pixmap.addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) info->pixmap.size = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) info->pixmap.buf_align = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) info->pixmap.scan_align = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) info->pixmap.access_align = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) info->pixmap.flags = FB_PIXMAP_SYSTEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) info->var.bits_per_pixel = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (default_par->image_blit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) info->pixmap.scan_align = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (noaccel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) printk(KERN_DEBUG "disabling acceleration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) info->flags |= FBINFO_HWACCEL_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) info->pixmap.scan_align = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (tridentfb_setup_ddc_bus(info) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) default_par->ddc_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) fb_edid_to_monspecs(edid, &info->monspecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) kfree(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (!info->monspecs.modedb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dev_err(info->device, "error getting mode database\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) const struct fb_videomode *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) fb_videomode_to_modelist(info->monspecs.modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) info->monspecs.modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) m = fb_find_best_display(&info->monspecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) fb_videomode_to_var(&info->var, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* fill all other info->var's fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (tridentfb_check_var(&info->var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) info) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (!mode_option && !found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) mode_option = "640x480-8@60";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* Prepare startup mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (mode_option) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) err = fb_find_mode(&info->var, info, mode_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) info->monspecs.modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) info->monspecs.modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) NULL, info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (!err || err == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) dev_err(info->device, "mode %s not found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) mode_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) fb_destroy_modedb(info->monspecs.modedb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) info->monspecs.modedb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) fb_destroy_modedb(info->monspecs.modedb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) info->monspecs.modedb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) err = fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) info->var.activate |= FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) info->device = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (register_framebuffer(info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) printk(KERN_ERR "tridentfb: could not register framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) info->node, info->fix.id, info->var.xres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) info->var.yres, info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pci_set_drvdata(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) out_unmap2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (default_par->ddc_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) i2c_del_adapter(&default_par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) kfree(info->pixmap.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) disable_mmio(info->par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) out_unmap1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (default_par->io_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) iounmap(default_par->io_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static void trident_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct fb_info *info = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct tridentfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (par->ddc_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) i2c_del_adapter(&par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) iounmap(par->io_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) kfree(info->pixmap.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* List of boards that we are trying to support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static const struct pci_device_id trident_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) MODULE_DEVICE_TABLE(pci, trident_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static struct pci_driver tridentfb_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .name = "tridentfb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .id_table = trident_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .probe = trident_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .remove = trident_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * Parse user specified options (`video=trident:')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * video=trident:800x600,bpp=16,noaccel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static int __init tridentfb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) char *opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) while ((opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (!*opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (!strncmp(opt, "noaccel", 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) noaccel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) else if (!strncmp(opt, "fp", 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) fp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) else if (!strncmp(opt, "crt", 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) fp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) else if (!strncmp(opt, "bpp=", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) bpp = simple_strtoul(opt + 4, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) else if (!strncmp(opt, "center", 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) center = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) else if (!strncmp(opt, "stretch", 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) stretch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) else if (!strncmp(opt, "memsize=", 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) memsize = simple_strtoul(opt + 8, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) else if (!strncmp(opt, "memdiff=", 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) memdiff = simple_strtoul(opt + 8, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) else if (!strncmp(opt, "nativex=", 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) nativex = simple_strtoul(opt + 8, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) mode_option = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static int __init tridentfb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (fb_get_options("tridentfb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) tridentfb_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return pci_register_driver(&tridentfb_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static void __exit tridentfb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) pci_unregister_driver(&tridentfb_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) module_init(tridentfb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) module_exit(tridentfb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) MODULE_ALIAS("cyblafb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags