^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * tdfxfb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Hannu Mallat <hmallat@cc.hut.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright © 1999 Hannu Mallat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Created : Thu Sep 23 18:17:43 1999, hmallat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Last modified: Tue Nov 2 21:19:47 1999, hmallat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * I2C part copied from the i2c-voodoo3.c driver by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Frodo Looijaard <frodol@dds.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Philip Edelbrock <phil@netroedge.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Ralph Metzler <rjkm@thp.uni-koeln.de>, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Mark D. Studebaker <mdsxyz123@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Lots of the information here comes from the Daryll Strauss' Banshee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * patches to the XF86 server, and the rest comes from the 3dfx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Banshee specification. I'm very much indebted to Daryll for his
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * work on the X server.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Voodoo3 support was contributed Harold Oga. Lots of additions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Kesmarki. Thanks guys!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * behave very differently from the Voodoo3/4/5. For anyone wanting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * located at http://www.sourceforge.net/projects/sstfb).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * I do wish the next version is a bit more complete. Without the XF86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * patches I couldn't have gotten even this far... for instance, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * extensions to the VGA register set go completely unmentioned in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * spec! Also, lots of references are made to the 'SST core', but no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * spec is publicly available, AFAIK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * The structure of this driver comes pretty much from the Permedia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * - multihead support (basically need to support an array of fb_infos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * - support other architectures (PPC, Alpha); does the fact that the VGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * core can be accessed only thru I/O (not memory mapped) complicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * things?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Version history:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 0.1.3 (released 1999-11-02) added Attila's panning support, code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * reorg, hwcursor address page size alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * (for mmapping both frame buffer and regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * and my changes to get rid of hardcoded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * VGA i/o register locations (uses PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * configuration info now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * improvements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 0.1.0 (released 1999-10-06) initial version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <video/tdfx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BANSHEE_MAX_PIXCLOCK 270000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VOODOO3_MAX_PIXCLOCK 300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VOODOO5_MAX_PIXCLOCK 350000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct fb_fix_screeninfo tdfx_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .visual = FB_VISUAL_PSEUDOCOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .ypanstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .ywrapstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .accel = FB_ACCEL_3DFX_BANSHEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct fb_var_screeninfo tdfx_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* "640x480, 8 bpp @ 60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .xres_virtual = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .yres_virtual = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .bits_per_pixel = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .red = {0, 8, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .blue = {0, 8, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .green = {0, 8, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .activate = FB_ACTIVATE_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .height = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .width = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .accel_flags = FB_ACCELF_TEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pixclock = 39722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .left_margin = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .right_margin = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .upper_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .lower_margin = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .hsync_len = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .vmode = FB_VMODE_NONINTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * PCI driver prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void tdfxfb_remove(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct pci_device_id tdfxfb_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0xff0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0xff0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0xff0000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct pci_driver tdfxfb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "tdfxfb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .id_table = tdfxfb_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .probe = tdfxfb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .remove = tdfxfb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int nopan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int nowrap = 1; /* not implemented (yet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int hwcursor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static char *mode_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static bool nomtrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* -------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Hardware-specific funcions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return inb(par->iobase + reg - 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) outb(val, par->iobase + reg - 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) vga_outb(par, GRA_I, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) vga_outb(par, GRA_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) vga_outb(par, SEQ_I, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) vga_outb(par, SEQ_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) vga_outb(par, SEQ_I, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return vga_inb(par, SEQ_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) vga_outb(par, CRT_I, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) vga_outb(par, CRT_D, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vga_outb(par, CRT_I, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return vga_inb(par, CRT_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tmp = vga_inb(par, IS1_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) vga_outb(par, ATT_IW, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) vga_outb(par, ATT_IW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline void vga_disable_video(struct tdfx_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned char s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) s = seq_inb(par, 0x01) | 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) seq_outb(par, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) seq_outb(par, 0x01, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) seq_outb(par, 0x00, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline void vga_enable_video(struct tdfx_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned char s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) s = seq_inb(par, 0x01) & 0xdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) seq_outb(par, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) seq_outb(par, 0x01, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) seq_outb(par, 0x00, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline void vga_enable_palette(struct tdfx_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) vga_inb(par, IS1_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) vga_outb(par, ATT_IW, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return readl(par->regbase_virt + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel(val, par->regbase_virt + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static inline void banshee_make_room(struct tdfx_par *par, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * won't quit if you ask for more. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int banshee_wait_idle(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) banshee_make_room(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } while (i < 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Set the color of a palette entry in 8bpp mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) banshee_make_room(par, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tdfx_outl(par, DACADDR, regno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* read after write makes it working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tdfx_inl(par, DACADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tdfx_outl(par, DACDATA, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static u32 do_calc_pll(int freq, int *freq_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int m, n, k, best_m, best_n, best_k, best_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int fref = 14318;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) best_error = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) best_n = best_m = best_k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (k = 3; k >= 0; k--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (m = 63; m >= 0; m--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Estimate value of n that produces target frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * with current m and k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Search neighborhood of estimated n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (n = max(0, n_estimated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) n <= min(255, n_estimated + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Calculate PLL freqency with current m, k and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * estimated n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int f = (fref * (n + 2) / (m + 2)) >> k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int error = abs(f - freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * If this is the closest we've come to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * target frequency then remember n, m and k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (error < best_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) best_error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) best_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) best_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) best_k = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) n = best_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) m = best_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) k = best_k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *freq_out = (fref * (n + 2) / (m + 2)) >> k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return (n << 8) | (m << 2) | k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) banshee_wait_idle(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) banshee_make_room(par, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tdfx_outl(par, PLLCTRL1, reg->mempll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tdfx_outl(par, PLLCTRL2, reg->gfxpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tdfx_outl(par, PLLCTRL0, reg->vidpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) seq_outb(par, i, reg->seq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < 25; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) crt_outb(par, i, reg->crt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < 9; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) gra_outb(par, i, reg->gra[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < 21; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) att_outb(par, i, reg->att[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) crt_outb(par, 0x1a, reg->ext[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) crt_outb(par, 0x1b, reg->ext[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) vga_enable_palette(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) vga_enable_video(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) banshee_make_room(par, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) tdfx_outl(par, VGAINIT0, reg->vgainit0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tdfx_outl(par, DACMODE, reg->dacmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tdfx_outl(par, VIDDESKSTART, reg->startaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tdfx_outl(par, VGAINIT1, reg->vgainit1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) tdfx_outl(par, MISCINIT0, reg->miscinit0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) banshee_make_room(par, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) tdfx_outl(par, SRCBASE, reg->startaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tdfx_outl(par, DSTBASE, reg->startaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tdfx_outl(par, COMMANDEXTRA_2D, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tdfx_outl(par, CLIP0MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tdfx_outl(par, CLIP1MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tdfx_outl(par, SRCXY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) banshee_wait_idle(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 draminit0 = tdfx_inl(par, DRAMINIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 draminit1 = tdfx_inl(par, DRAMINIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 miscinit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int chip_size; /* in MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Banshee/Voodoo3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) chip_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) chip_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Voodoo4/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) has_sgram = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* disable block writes for SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) miscinit1 = tdfx_inl(par, MISCINIT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) miscinit1 |= MISCINIT1_CLUT_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) banshee_make_room(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tdfx_outl(par, MISCINIT1, miscinit1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return num_chips * chip_size * 1024l * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 lpitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (var->xres != var->xres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (var->yres > var->yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (var->xoffset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DPRINTK("xoffset not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) var->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Banshee doesn't support interlace, but Voodoo4/5 and probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Voodoo3 do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * no direct information about device id now?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * use max_pixclock for this...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DPRINTK("interlace not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (info->monspecs.hfmax && info->monspecs.vfmax &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DPRINTK("mode outside monitor's specs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (var->xres < 320 || var->xres > 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DPRINTK("width not supported: %u\n", var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (var->yres < 200 || var->yres > 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DPRINTK("height not supported: %u\n", var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (lpitch * var->yres_virtual > info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) var->yres_virtual = info->fix.smem_len / lpitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (var->yres_virtual < var->yres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DPRINTK("no memory for screen (%ux%ux%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) var->xres, var->yres_virtual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DPRINTK("pixclock too high (%ldKHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PICOS2KHZ(var->pixclock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) var->transp.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) var->red.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) var->green = var->red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) var->blue = var->red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) var->red.offset = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) var->green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) var->red.length = var->green.length = var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) var->width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) var->height = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) var->accel_flags = FB_ACCELF_TEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) DPRINTK("Checking graphics mode at %dx%d depth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) var->xres, var->yres, var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int tdfxfb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 hdispend = info->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 hsyncsta = hdispend + info->var.right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 hsyncend = hsyncsta + info->var.hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 htotal = hsyncend + info->var.left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 hd, hs, he, ht, hbs, hbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 vd, vs, ve, vt, vbs, vbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct banshee_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int fout, freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) memset(®, 0, sizeof(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) VIDCFG_CURS_X11 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* PLL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) freq = PICOS2KHZ(info->var.pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg.vidcfg &= ~VIDCFG_2X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (freq > par->max_pixclock / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) freq = freq > par->max_pixclock ? par->max_pixclock : freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) reg.dacmode |= DACMODE_2X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) reg.vidcfg |= VIDCFG_2X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) hdispend >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hsyncsta >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hsyncend >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) htotal >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) wd = (hdispend >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hd = wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hs = (hsyncsta >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) he = (hsyncend >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ht = (htotal >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) hbs = hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hbe = ht;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) vd = (info->var.yres << 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) vs = vd + (info->var.lower_margin << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ve = vs + (info->var.vsync_len << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) vt = ve + (info->var.upper_margin << 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) reg.screensize = info->var.xres | (info->var.yres << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg.vidcfg |= VIDCFG_HALF_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) reg.crt[0x09] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) vd = info->var.yres - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) vs = vd + info->var.lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ve = vs + info->var.vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) vt = ve + info->var.upper_margin - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) reg.screensize = info->var.xres | (info->var.yres << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) reg.vidcfg &= ~VIDCFG_HALF_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) vbs = vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vbe = vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* this is all pretty standard VGA register stuffing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) reg.misc[0x00] = 0x0f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (info->var.xres < 400 ? 0xa0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) info->var.xres < 480 ? 0x60 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) info->var.xres < 768 ? 0xe0 : 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) reg.gra[0x05] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) reg.gra[0x06] = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) reg.gra[0x07] = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reg.gra[0x08] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) reg.att[0x00] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) reg.att[0x01] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) reg.att[0x02] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) reg.att[0x03] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reg.att[0x04] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) reg.att[0x05] = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) reg.att[0x06] = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg.att[0x07] = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) reg.att[0x08] = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) reg.att[0x09] = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) reg.att[0x0a] = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) reg.att[0x0b] = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) reg.att[0x0c] = 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) reg.att[0x0d] = 0x0d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) reg.att[0x0e] = 0x0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) reg.att[0x0f] = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) reg.att[0x10] = 0x41;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) reg.att[0x12] = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) reg.seq[0x00] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) reg.seq[0x02] = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) reg.seq[0x03] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) reg.seq[0x04] = 0x0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) reg.crt[0x00] = ht - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) reg.crt[0x01] = hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) reg.crt[0x02] = hbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) reg.crt[0x03] = 0x80 | (hbe & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) reg.crt[0x04] = hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) reg.crt[0x06] = vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) reg.crt[0x07] = ((vs & 0x200) >> 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ((vd & 0x200) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ((vt & 0x200) >> 4) | 0x10 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ((vbs & 0x100) >> 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ((vs & 0x100) >> 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ((vd & 0x100) >> 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ((vt & 0x100) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) reg.crt[0x10] = vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) reg.crt[0x11] = (ve & 0x0f) | 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) reg.crt[0x12] = vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) reg.crt[0x13] = wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) reg.crt[0x15] = vbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) reg.crt[0x16] = vbe + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) reg.crt[0x17] = 0xc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) reg.crt[0x18] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Banshee's nonvga stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) reg.ext[0x00] = (((ht & 0x100) >> 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ((hd & 0x100) >> 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ((hbs & 0x100) >> 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ((hbe & 0x40) >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ((hs & 0x100) >> 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ((he & 0x20) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) reg.ext[0x01] = (((vt & 0x400) >> 10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ((vd & 0x400) >> 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ((vbs & 0x400) >> 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ((vbe & 0x400) >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) reg.vgainit0 = VGAINIT0_8BIT_DAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) VGAINIT0_EXT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) VGAINIT0_WAKEUP_3C3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) VGAINIT0_ALT_READBACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) VGAINIT0_EXTSHIFTOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (hwcursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) reg.curspataddr = info->fix.smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) reg.cursloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) reg.cursc0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) reg.cursc1 = 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) reg.stride = info->var.xres * cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) reg.startaddr = info->var.yoffset * reg.stride
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) + info->var.xoffset * cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) reg.vidpll = do_calc_pll(freq, &fout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) reg.mempll = do_calc_pll(..., &fout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) reg.gfxpll = do_calc_pll(..., &fout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) reg.vidcfg |= VIDCFG_INTERLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) reg.miscinit0 = tdfx_inl(par, MISCINIT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) switch (info->var.bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) reg.miscinit0 &= ~(1 << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) reg.miscinit0 &= ~(1 << 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) reg.miscinit0 |= (1 << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) reg.miscinit0 |= (1 << 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) reg.miscinit0 |= (1 << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) reg.miscinit0 &= ~(1 << 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) do_write_regs(info, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Now change fb_fix_screeninfo according to changes in par */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) info->fix.line_length = reg.stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) info->fix.visual = (info->var.bits_per_pixel == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ? FB_VISUAL_PSEUDOCOLOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) : FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) info->var.xres, info->var.yres, info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* A handy macro shamelessly pinched from matroxfb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unsigned blue, unsigned transp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 rgbcol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (regno >= info->cmap.len || regno > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* grayscale works only partially under directcolor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (info->var.grayscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* grayscale = 0.30*R + 0.59*G + 0.11*B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) blue = (red * 77 + green * 151 + blue * 28) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) green = blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) red = blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) switch (info->fix.visual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case FB_VISUAL_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rgbcol = (((u32)red & 0xff00) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (((u32)green & 0xff00) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) (((u32)blue & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) do_setpalentry(par, regno, rgbcol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Truecolor has no hardware color palettes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case FB_VISUAL_TRUECOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) info->var.red.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) (CNVT_TOHW(green, info->var.green.length) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) info->var.green.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) (CNVT_TOHW(blue, info->var.blue.length) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) info->var.blue.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (CNVT_TOHW(transp, info->var.transp.length) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) info->var.transp.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) par->palette[regno] = rgbcol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int tdfxfb_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int vgablank = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 dacmode = tdfx_inl(par, DACMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dacmode &= ~(BIT(1) | BIT(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) switch (blank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) vgablank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dacmode |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dacmode |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dacmode |= BIT(1) | BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) banshee_make_room(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) tdfx_outl(par, DACMODE, dacmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (vgablank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) vga_disable_video(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) vga_enable_video(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * Set the starting position of the visible screen to var->yoffset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 addr = var->yoffset * info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (nopan || var->xoffset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) banshee_make_room(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) tdfx_outl(par, VIDDESKSTART, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #ifdef CONFIG_FB_3DFX_ACCEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * FillRect 2D command (solidfill or invert (via ROP_XOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static void tdfxfb_fillrect(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) const struct fb_fillrect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 bpp = info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 stride = info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int tdfx_rop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 dx = rect->dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u32 dy = rect->dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 dstbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (rect->rop == ROP_COPY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) tdfx_rop = TDFX_ROP_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) tdfx_rop = TDFX_ROP_XOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* assume always rect->height < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (dy + rect->height > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dstbase = stride * dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* assume always rect->width < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (dx + rect->width > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dstbase += dx * bpp >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) banshee_make_room(par, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) tdfx_outl(par, DSTFORMAT, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) tdfx_outl(par, COLORFORE, rect->color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } else { /* FB_VISUAL_TRUECOLOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) tdfx_outl(par, COLORFORE, par->palette[rect->color]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) tdfx_outl(par, DSTBASE, dstbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void tdfxfb_copyarea(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) const struct fb_copyarea *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u32 bpp = info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u32 stride = info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 dstbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 srcbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* assume always area->height < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (sy + area->height > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) srcbase = stride * sy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) sy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* assume always area->width < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (sx + area->width > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) srcbase += sx * bpp >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) sx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* assume always area->height < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (dy + area->height > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dstbase = stride * dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* assume always area->width < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (dx + area->width > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dstbase += dx * bpp >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (area->sx <= area->dx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* -X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) blitcmd |= BIT(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) sx += area->width - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dx += area->width - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (area->sy <= area->dy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* -Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) blitcmd |= BIT(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) sy += area->height - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dy += area->height - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) banshee_make_room(par, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) tdfx_outl(par, SRCFORMAT, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) tdfx_outl(par, DSTFORMAT, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) tdfx_outl(par, COMMAND_2D, blitcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) tdfx_outl(par, DSTXY, dx | (dy << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) tdfx_outl(par, SRCBASE, srcbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) tdfx_outl(par, DSTBASE, dstbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int size = image->height * ((image->width * image->depth + 7) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int fifo_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) int i, stride = info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u32 bpp = info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u8 *chardata = (u8 *) image->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 srcfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u32 dx = image->dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u32 dy = image->dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u32 dstbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (image->depth != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #ifdef BROKEN_CODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) banshee_make_room(par, 6 + ((size + 3) >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) cfb_imageblit(info, image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) banshee_make_room(par, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) switch (info->fix.visual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case FB_VISUAL_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) tdfx_outl(par, COLORFORE, image->fg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) tdfx_outl(par, COLORBACK, image->bg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case FB_VISUAL_TRUECOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) tdfx_outl(par, COLORFORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) par->palette[image->fg_color]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) tdfx_outl(par, COLORBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) par->palette[image->bg_color]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) srcfmt = 0x400000 | BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) srcfmt = 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* assume always image->height < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (dy + image->height > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dstbase = stride * dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* assume always image->width < 4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (dx + image->width > 4095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dstbase += dx * bpp >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) tdfx_outl(par, DSTBASE, dstbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) tdfx_outl(par, SRCXY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) tdfx_outl(par, DSTXY, dx | (dy << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) tdfx_outl(par, COMMAND_2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) tdfx_outl(par, SRCFORMAT, srcfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) tdfx_outl(par, DSTFORMAT, dstfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* A count of how many free FIFO entries we've requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * When this goes negative, we need to request more. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fifo_free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Send four bytes at a time of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) for (i = (size >> 2); i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (--fifo_free < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) fifo_free = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) banshee_make_room(par, fifo_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) chardata += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Send the leftovers now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) banshee_make_room(par, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) switch (size % 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) tdfx_outl(par, LAUNCH_2D, *chardata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) tdfx_outl(par, LAUNCH_2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) *(u16 *)chardata | (chardata[3] << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #endif /* CONFIG_FB_3DFX_ACCEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) u32 vidcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (!hwcursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return -EINVAL; /* just to force soft_cursor() call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* Too large of a cursor or wrong bpp :-( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (cursor->image.width > 64 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) cursor->image.height > 64 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cursor->image.depth > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) vidcfg = tdfx_inl(par, VIDPROCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (cursor->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * If the cursor is not be changed this means either we want the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * current cursor state (if enable is set) or we want to query what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * we can do with the cursor (if enable is not set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (!cursor->set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* fix cursor color - XFree86 forgets to restore it properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (cursor->set & FB_CUR_SETCMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct fb_cmap cmap = info->cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u32 bg_idx = cursor->image.bg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 fg_idx = cursor->image.fg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) unsigned long bg_color, fg_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (((u32)cmap.green[fg_idx] & 0xff00) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) (((u32)cmap.blue[fg_idx] & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) (((u32)cmap.green[bg_idx] & 0xff00) << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) (((u32)cmap.blue[bg_idx] & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) banshee_make_room(par, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) tdfx_outl(par, HWCURC0, bg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) tdfx_outl(par, HWCURC1, fg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (cursor->set & FB_CUR_SETPOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int x = cursor->image.dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int y = cursor->image.dy - info->var.yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) x += 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) y += 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) banshee_make_room(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) tdfx_outl(par, HWCURLOC, (y << 16) + x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * Voodoo 3 and above cards use 2 monochrome cursor patterns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * The reason is so the card can fetch 8 words at a time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * and are stored on chip for use for the next 8 scanlines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * This reduces the number of times for access to draw the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * cursor for each screen refresh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * Each pattern is a bitmap of 64 bit wide and 64 bit high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * (total of 8192 bits or 1024 bytes). The two patterns are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * stored in such a way that pattern 0 always resides in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * lower half (least significant 64 bits) of a 128 bit word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * and pattern 1 the upper half. If you examine the data of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * the cursor image the graphics card uses then from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * beginning you see line one of pattern 0, line one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * pattern 1, line two of pattern 0, line two of pattern 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * etc etc. The linear stride for the cursor is always 16 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * (128 bits) which is the maximum cursor width times two for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * the two monochrome patterns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u8 *bitmap = (u8 *)cursor->image.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u8 *mask = (u8 *)cursor->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) fb_memset(cursorbase, 0, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) for (i = 0; i < cursor->image.height; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int j = (cursor->image.width + 7) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) for (; j > 0; j--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u8 data = *mask ^ *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (cursor->rop == ROP_COPY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) data = *mask & *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Pattern 0. Copy the cursor mask to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) fb_writeb(*mask, cursorbase + h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mask++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Pattern 1. Copy the cursor bitmap to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fb_writeb(data, cursorbase + h + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) bitmap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) h++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) cursorbase += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct fb_ops tdfxfb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .fb_check_var = tdfxfb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .fb_set_par = tdfxfb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .fb_setcolreg = tdfxfb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .fb_blank = tdfxfb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .fb_pan_display = tdfxfb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .fb_sync = banshee_wait_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .fb_cursor = tdfxfb_cursor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #ifdef CONFIG_FB_3DFX_ACCEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .fb_fillrect = tdfxfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .fb_copyarea = tdfxfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .fb_imageblit = tdfxfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #ifdef CONFIG_FB_3DFX_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* The voo GPIO registers don't have individual masks for each bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) so we always have to read before writing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static void tdfxfb_i2c_setscl(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) unsigned int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) r = tdfx_inl(par, VIDSERPARPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) r |= I2C_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) r &= ~I2C_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) tdfx_outl(par, VIDSERPARPORT, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static void tdfxfb_i2c_setsda(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unsigned int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) r = tdfx_inl(par, VIDSERPARPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) r |= I2C_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) r &= ~I2C_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) tdfx_outl(par, VIDSERPARPORT, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* The GPIO pins are open drain, so the pins always remain outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) We rely on the i2c-algo-bit routines to set the pins high before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) reading the input from other chips. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int tdfxfb_i2c_getscl(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int tdfxfb_i2c_getsda(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static void tdfxfb_ddc_setscl(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) r = tdfx_inl(par, VIDSERPARPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) r |= DDC_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) r &= ~DDC_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) tdfx_outl(par, VIDSERPARPORT, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static void tdfxfb_ddc_setsda(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) r = tdfx_inl(par, VIDSERPARPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) r |= DDC_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) r &= ~DDC_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) tdfx_outl(par, VIDSERPARPORT, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int tdfxfb_ddc_getscl(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int tdfxfb_ddc_getsda(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct tdfxfb_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct tdfx_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) chan->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) chan->adapter.class = I2C_CLASS_DDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) chan->adapter.algo_data = &chan->algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) chan->adapter.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) chan->algo.setsda = tdfxfb_ddc_setsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) chan->algo.setscl = tdfxfb_ddc_setscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) chan->algo.getsda = tdfxfb_ddc_getsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) chan->algo.getscl = tdfxfb_ddc_getscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) chan->algo.udelay = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) chan->algo.timeout = msecs_to_jiffies(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) chan->algo.data = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) i2c_set_adapdata(&chan->adapter, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) rc = i2c_bit_add_bus(&chan->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) DPRINTK("I2C bus %s registered.\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) chan->par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) chan->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) chan->adapter.algo_data = &chan->algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) chan->adapter.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) chan->algo.setsda = tdfxfb_i2c_setsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) chan->algo.setscl = tdfxfb_i2c_setscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) chan->algo.getsda = tdfxfb_i2c_getsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) chan->algo.getscl = tdfxfb_i2c_getscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) chan->algo.udelay = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) chan->algo.timeout = msecs_to_jiffies(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) chan->algo.data = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) i2c_set_adapdata(&chan->adapter, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) rc = i2c_bit_add_bus(&chan->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) DPRINTK("I2C bus %s registered.\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) chan->par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static void tdfxfb_create_i2c_busses(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) tdfx_outl(par, VIDINFORMAT, 0x8160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) par->chan[0].par = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) par->chan[1].par = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (par->chan[0].par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) i2c_del_adapter(&par->chan[0].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) par->chan[0].par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (par->chan[1].par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) i2c_del_adapter(&par->chan[1].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) par->chan[1].par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct fb_monspecs *specs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u8 *edid = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) DPRINTK("Probe DDC Bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (par->chan[0].par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) edid = fb_ddc_read(&par->chan[0].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) fb_edid_to_monspecs(edid, specs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) kfree(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #endif /* CONFIG_FB_3DFX_I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * tdfxfb_probe - Device Initializiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * @pdev: PCI Device to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * @id: PCI Device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * Initializes and allocates resources for PCI device @pdev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct tdfx_par *default_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) int err, lpitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct fb_monspecs *specs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) bool found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) default_par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) info->fix = tdfx_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* Configure the default fb_fix_screeninfo first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) case PCI_DEVICE_ID_3DFX_BANSHEE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) strcpy(info->fix.id, "3Dfx Banshee");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case PCI_DEVICE_ID_3DFX_VOODOO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) strcpy(info->fix.id, "3Dfx Voodoo3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case PCI_DEVICE_ID_3DFX_VOODOO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) strcpy(info->fix.id, "3Dfx Voodoo5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) info->fix.mmio_start = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) info->fix.mmio_len = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) "tdfx regbase")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) default_par->regbase_virt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ioremap(info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!default_par->regbase_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) printk(KERN_ERR "fb: Can't remap %s register area.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) goto out_err_regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) info->fix.smem_start = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) info->fix.smem_len = do_lfb_size(default_par, pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (!info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) goto out_err_regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (!request_mem_region(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pci_resource_len(pdev, 1), "tdfx smem")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto out_err_regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) info->screen_base = ioremap_wc(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) goto out_err_screenbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) default_par->iobase = pci_resource_start(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (!request_region(pci_resource_start(pdev, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) pci_resource_len(pdev, 2), "tdfx iobase")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) goto out_err_screenbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) info->fix.smem_len >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (!nomtrr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) info->fix.ypanstep = nopan ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) info->fix.ywrapstep = nowrap ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) info->fbops = &tdfxfb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) info->pseudo_palette = default_par->palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #ifdef CONFIG_FB_3DFX_ACCEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) info->flags |= FBINFO_HWACCEL_FILLRECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) FBINFO_HWACCEL_COPYAREA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) FBINFO_HWACCEL_IMAGEBLIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) FBINFO_READS_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* reserve 8192 bits for cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (hwcursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) info->fix.smem_len = (info->fix.smem_len - 1024) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) (PAGE_MASK << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) specs = &info->monspecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) info->var.bits_per_pixel = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #ifdef CONFIG_FB_3DFX_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) tdfxfb_create_i2c_busses(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) err = tdfxfb_probe_i2c_connector(default_par, specs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (specs->modedb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) DPRINTK("Unable to get Mode Database\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) const struct fb_videomode *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) fb_videomode_to_modelist(specs->modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) specs->modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) m = fb_find_best_display(specs, &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) fb_videomode_to_var(&info->var, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* fill all other info->var's fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (tdfxfb_check_var(&info->var, info) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) info->var = tdfx_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (!mode_option && !found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) mode_option = "640x480@60";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (mode_option) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) err = fb_find_mode(&info->var, info, mode_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) specs->modedb, specs->modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) NULL, info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!err || err == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) info->var = tdfx_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) fb_destroy_modedb(specs->modedb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) specs->modedb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* maximize virtual vertical length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) info->var.yres_virtual = info->fix.smem_len / lpitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (info->var.yres_virtual < info->var.yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) goto out_err_iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) goto out_err_iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (register_framebuffer(info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) goto out_err_iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * Our driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pci_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) out_err_iobase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #ifdef CONFIG_FB_3DFX_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) tdfxfb_delete_i2c_busses(default_par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) arch_phys_wc_del(default_par->wc_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) release_region(pci_resource_start(pdev, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) pci_resource_len(pdev, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) out_err_screenbase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) out_err_regbase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * Cleanup after anything that was remapped/allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (default_par->regbase_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) iounmap(default_par->regbase_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static void __init tdfxfb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) char *this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) while ((this_opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (!*this_opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (!strcmp(this_opt, "nopan")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) nopan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) } else if (!strcmp(this_opt, "nowrap")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) nowrap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) } else if (!strncmp(this_opt, "hwcursor=", 9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) } else if (!strncmp(this_opt, "nomtrr", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) nomtrr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) mode_option = this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * tdfxfb_remove - Device removal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * @pdev: PCI Device to cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) * Releases all resources allocated during the course of the driver's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * lifetime for the PCI device @pdev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static void tdfxfb_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct fb_info *info = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct tdfx_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #ifdef CONFIG_FB_3DFX_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) tdfxfb_delete_i2c_busses(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) arch_phys_wc_del(par->wc_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) iounmap(par->regbase_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Clean up after reserved regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) release_region(pci_resource_start(pdev, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pci_resource_len(pdev, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) release_mem_region(pci_resource_start(pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pci_resource_len(pdev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) release_mem_region(pci_resource_start(pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pci_resource_len(pdev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static int __init tdfxfb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (fb_get_options("tdfxfb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) tdfxfb_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return pci_register_driver(&tdfxfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static void __exit tdfxfb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) pci_unregister_driver(&tdfxfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) MODULE_DESCRIPTION("3Dfx framebuffer device driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) module_param(hwcursor, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) "(1=enable, 0=disable, default=1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) module_param(mode_option, charp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) module_param(nomtrr, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) module_init(tdfxfb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) module_exit(tdfxfb_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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