^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/stifb.c -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Low level Frame buffer driver for HP workstations with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * STI (standard text interface) video firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001-2006 Helge Deller <deller@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Portions Copyright (C) 2001 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - linux/drivers/video/artistfb.c -- Artist frame buffer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - based on skeletonfb, which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Created 28 Dec 1997 by Geert Uytterhoeven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - HP Xhp cfb-based X11 window driver for XFree86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * (c)Copyright 1992 Hewlett-Packard Co.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * The following graphics display devices (NGLE family) are supported by this driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * HPA4070A known as "HCRX", a 1280x1024 color device with 8 planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * HPA4071A known as "HCRX24", a 1280x1024 color device with 24 planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * optionally available with a hardware accelerator as HPA4071A_Z
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * HPA1659A known as "CRX", a 1280x1024 color device with 8 planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * HPA1439A known as "CRX24", a 1280x1024 color device with 24 planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * optionally available with a hardware accelerator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * HPA1924A known as "GRX", a 1280x1024 grayscale device with 8 planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * HPA2269A known as "Dual CRX", a 1280x1024 color device with 8 planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * implements support for two displays on a single graphics card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * HP710C internal graphics support optionally available on the HP9000s710 SPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * supports 1280x1024 color displays with 8 planes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * HP710G same as HP710C, 1280x1024 grayscale only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * HP710L same as HP710C, 1024x768 color only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * HP712 internal graphics support on HP9000s712 SPU, supports 640x480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 1024x768 or 1280x1024 color displays on 8 planes (Artist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - 1bpp mode is completely untested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * - add support for h/w acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * - add hardware cursor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * - automatically disable double buffering (e.g. on RDI precisionbook laptop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* on supported graphic devices you may:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * #define FALLBACK_TO_1BPP to fall back to 1 bpp, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * #undef FALLBACK_TO_1BPP to reject support for unsupported cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #undef FALLBACK_TO_1BPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #undef DEBUG_STIFB_REGS /* debug sti register accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <asm/grfioctl.h> /* for HP-UX compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include "sticore.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* REGION_BASE(fb_info, index) returns the virtual address for region <index> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REGION_BASE(fb_info, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) F_EXTEND(fb_info->sti->glob_cfg->region_ptrs[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NGLEDEVDEPROM_CRT_REGION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NR_PALETTE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __s32 video_config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __s32 misc_video_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __s32 horiz_timing_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __s32 serr_timing_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __s32 vert_timing_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __s32 horiz_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __s32 vert_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __s32 vtg_state_elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __s32 pipeline_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __s32 misc_video_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } video_setup_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __s16 sizeof_ngle_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __s16 x_size_visible; /* visible screen dim in pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __s16 y_size_visible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __s16 pad2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __s16 cursor_pipeline_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __s16 video_interleaves;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __s32 pad3[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } ngle_rom_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct stifb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct fb_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ngle_rom_t ngle_rom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct sti_struct *sti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int deviceSpecificConfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* ------------------- chipset specific functions -------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* offsets to graphic-chip internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define REG_1 0x000118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define REG_2 0x000480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define REG_3 0x0004a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define REG_4 0x000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define REG_6 0x000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define REG_7 0x000804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REG_8 0x000820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define REG_9 0x000a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_10 0x018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define REG_11 0x018004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define REG_12 0x01800c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define REG_13 0x018018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_14 0x01801c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define REG_15 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define REG_15b0 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define REG_16b1 0x200005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define REG_16b3 0x200007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define REG_21 0x200218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_22 0x0005a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define REG_23 0x0005c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define REG_24 0x000808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define REG_25 0x000b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REG_26 0x200118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define REG_27 0x200308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REG_32 0x21003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REG_33 0x210040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define REG_34 0x200008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define REG_35 0x018010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REG_38 0x210020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define REG_39 0x210120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define REG_40 0x210130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define REG_42 0x210028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define REG_43 0x21002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define REG_44 0x210030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define REG_45 0x210034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define READ_BYTE(fb,reg) gsc_readb((fb)->info.fix.mmio_start + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define READ_WORD(fb,reg) gsc_readl((fb)->info.fix.mmio_start + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifndef DEBUG_STIFB_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define DEBUG_OFF()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define DEBUG_ON()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define WRITE_BYTE(value,fb,reg) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define WRITE_WORD(value,fb,reg) gsc_writel((value),(fb)->info.fix.mmio_start + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int debug_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define DEBUG_OFF() debug_on=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define DEBUG_ON() debug_on=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define WRITE_BYTE(value,fb,reg) do { if (debug_on) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __func__, reg, value, READ_BYTE(fb,reg)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define WRITE_WORD(value,fb,reg) do { if (debug_on) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __func__, reg, value, READ_WORD(fb,reg)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gsc_writel((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif /* DEBUG_STIFB_REGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ENABLE 1 /* for enabling/disabling screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define NGLE_LOCK(fb_info) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define NGLE_UNLOCK(fb_info) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SETUP_HW(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) char stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) stat = READ_BYTE(fb, REG_15b0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) stat = READ_BYTE(fb, REG_15b0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } while (stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SETUP_FB(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int reg10_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) switch (fb->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case CRT_ID_VISUALIZE_EG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case S9000_ID_ARTIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case S9000_ID_A1659A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg10_value = 0x13601000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case S9000_ID_A1439A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (fb->info.var.bits_per_pixel == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg10_value = 0xBBA0A000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg10_value = 0x13601000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case S9000_ID_HCRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (fb->info.var.bits_per_pixel == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg10_value = 0xBBA0A000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg10_value = 0x13602000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case S9000_ID_TIMBER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case CRX24_OVERLAY_PLANES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg10_value = 0x13602000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (reg10_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) WRITE_WORD(reg10_value, fb, REG_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) WRITE_WORD(0x83000300, fb, REG_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) WRITE_BYTE(1, fb, REG_16b1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) START_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) WRITE_WORD(0xBBE0F000, fb, REG_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) WRITE_WORD(0x03000300, fb, REG_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) WRITE_WORD(~0, fb, REG_13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) WRITE_IMAGE_COLOR(struct stifb_info *fb, int index, int color)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) WRITE_WORD(((0x100+index)<<2), fb, REG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) WRITE_WORD(color, fb, REG_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) FINISH_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) WRITE_WORD(0x400, fb, REG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (fb->info.var.bits_per_pixel == 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) WRITE_WORD(0x83000100, fb, REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (fb->id == S9000_ID_ARTIST || fb->id == CRT_ID_VISUALIZE_EG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) WRITE_WORD(0x80000100, fb, REG_26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) WRITE_WORD(0x80000100, fb, REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SETUP_RAMDAC(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) WRITE_WORD(0x04000000, fb, 0x1020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) WRITE_WORD(0xff000000, fb, 0x1028);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CRX24_SETUP_RAMDAC(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) WRITE_WORD(0x04000000, fb, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) WRITE_WORD(0x02000000, fb, 0x1004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) WRITE_WORD(0xff000000, fb, 0x1008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) WRITE_WORD(0x05000000, fb, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) WRITE_WORD(0x02000000, fb, 0x1004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) WRITE_WORD(0x03000000, fb, 0x1008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) HCRX_SETUP_RAMDAC(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) WRITE_WORD(0xffffffff, fb, REG_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) CRX24_SET_OVLY_MASK(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) WRITE_WORD(0x13a02000, fb, REG_11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) WRITE_WORD(0x03000300, fb, REG_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) WRITE_WORD(0x000017f0, fb, REG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) WRITE_WORD(0xffffffff, fb, REG_13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WRITE_WORD(0xffffffff, fb, REG_22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) WRITE_WORD(0x00000000, fb, REG_23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int value = enable ? 0x43000000 : 0x03000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) WRITE_WORD(0x06000000, fb, 0x1030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) WRITE_WORD(value, fb, 0x1038);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CRX24_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int value = enable ? 0x10000000 : 0x30000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) WRITE_WORD(0x01000000, fb, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) WRITE_WORD(0x02000000, fb, 0x1004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) WRITE_WORD(value, fb, 0x1008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ARTIST_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 DregsMiscVideo = REG_21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 DregsMiscCtl = REG_27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) WRITE_WORD(READ_WORD(fb, DregsMiscVideo) | 0x0A000000, fb, DregsMiscVideo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) WRITE_WORD(READ_WORD(fb, DregsMiscCtl) | 0x00800000, fb, DregsMiscCtl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) WRITE_WORD(READ_WORD(fb, DregsMiscVideo) & ~0x0A000000, fb, DregsMiscVideo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) WRITE_WORD(READ_WORD(fb, DregsMiscCtl) & ~0x00800000, fb, DregsMiscCtl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define GET_ROMTABLE_INDEX(fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (READ_BYTE(fb, REG_16b3) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HYPER_CONFIG_PLANES_24 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IS_24_DEVICE(fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (fb->deviceSpecificConfig & HYPER_CONFIG_PLANES_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IS_888_DEVICE(fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (!(IS_24_DEVICE(fb)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GET_FIFO_SLOTS(fb, cnt, numslots) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { while (cnt < numslots) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cnt = READ_WORD(fb, REG_34); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cnt -= numslots; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IndexedDcd 0 /* Pixel data is indexed (pseudo) color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define Otc04 2 /* Pixels in each longword transfer (4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define Otc32 5 /* Pixels in each longword transfer (32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define Ots08 3 /* Each pixel is size (8)d transfer (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OtsIndirect 6 /* Each bit goes through FG/BG color(8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AddrLong 5 /* FB address is Long aligned (pixel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define BINovly 0x2 /* 8 bit overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define BINapp0I 0x0 /* Application Buffer 0, Indexed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define BINapp1I 0x1 /* Application Buffer 1, Indexed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define BINapp0F8 0xa /* Application Buffer 0, Fractional 8-8-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BINattr 0xd /* Attribute Bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define RopSrc 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BitmapExtent08 3 /* Each write hits ( 8) bits in depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define BitmapExtent32 5 /* Each write hits (32) bits in depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DataDynamic 0 /* Data register reloaded by direct access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MaskDynamic 1 /* Mask register reloaded by direct access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MaskOtc 0 /* Mask contains Object Count valid bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MaskAddrOffset(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define StaticReg(en) (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define BGx(en) (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define FGx(en) (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define BAJustPoint(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define BAIndexBase(base) (base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define BA(F,C,S,A,J,B,I) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (((F)<<31)|((C)<<27)|((S)<<24)|((A)<<21)|((J)<<16)|((B)<<12)|(I))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IBOvals(R,M,X,S,D,L,B,F) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (((R)<<8)|((M)<<16)|((X)<<24)|((S)<<29)|((D)<<28)|((L)<<31)|((B)<<1)|(F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WRITE_WORD(val, fb, REG_14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define NGLE_QUICK_SET_DST_BM_ACCESS(fb, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) WRITE_WORD(val, fb, REG_11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define NGLE_QUICK_SET_CTL_PLN_REG(fb, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) WRITE_WORD(val, fb, REG_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, plnmsk32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) WRITE_WORD(plnmsk32, fb, REG_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, fg32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) WRITE_WORD(fg32, fb, REG_35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define NGLE_SET_TRANSFERDATA(fb, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) WRITE_WORD(val, fb, REG_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define NGLE_SET_DSTXY(fb, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) WRITE_WORD(val, fb, REG_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define NGLE_LONG_FB_ADDRESS(fbaddrbase, x, y) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) (u32) (fbaddrbase) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ( (unsigned int) ( (y) << 13 ) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) (unsigned int) ( (x) << 2 ) ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define NGLE_BINC_SET_DSTADDR(fb, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) WRITE_WORD(addr, fb, REG_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define NGLE_BINC_SET_SRCADDR(fb, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) WRITE_WORD(addr, fb, REG_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define NGLE_BINC_SET_DSTMASK(fb, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) WRITE_WORD(mask, fb, REG_22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define NGLE_BINC_WRITE32(fb, data32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) WRITE_WORD(data32, fb, REG_23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define START_COLORMAPLOAD(fb, cmapBltCtlData32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) WRITE_WORD((cmapBltCtlData32), fb, REG_38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SET_LENXY_START_RECFILL(fb, lenxy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) WRITE_WORD(lenxy, fb, REG_9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SETUP_COPYAREA(fb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) WRITE_BYTE(0, fb, REG_16b1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) HYPER_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 DregsHypMiscVideo = REG_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) value = READ_WORD(fb, DregsHypMiscVideo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) value |= 0x0A000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) value &= ~0x0A000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) WRITE_WORD(value, fb, DregsHypMiscVideo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* BufferNumbers used by SETUP_ATTR_ACCESS() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define BUFF0_CMAP0 0x00001e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define BUFF1_CMAP0 0x02001e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define BUFF1_CMAP3 0x0c001e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define ARTIST_CMAP0 0x00000102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HYPER_CMAP8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HYPER_CMAP24 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SETUP_ATTR_ACCESS(struct stifb_info *fb, unsigned BufferNumber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) WRITE_WORD(0x2EA0D000, fb, REG_11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) WRITE_WORD(0x23000302, fb, REG_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) WRITE_WORD(BufferNumber, fb, REG_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) WRITE_WORD(0xffffffff, fb, REG_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SET_ATTR_SIZE(struct stifb_info *fb, int width, int height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* REG_6 seems to have special values when run on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RDI precisionbook parisc laptop (INTERNAL_EG_DX1024 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) INTERNAL_EG_X1024). The values are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0x2f0: internal (LCD) & external display enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x2a0: external display only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x000: zero on standard artist graphic cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) WRITE_WORD(0x00000000, fb, REG_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) WRITE_WORD((width<<16) | height, fb, REG_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) WRITE_WORD(0x05000000, fb, REG_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) WRITE_WORD(0x00040001, fb, REG_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) FINISH_ATTR_ACCESS(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) WRITE_WORD(0x00000000, fb, REG_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) elkSetupPlanes(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SETUP_RAMDAC(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ngleSetupAttrPlanes(struct stifb_info *fb, int BufferNumber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SETUP_ATTR_ACCESS(fb, BufferNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SET_ATTR_SIZE(fb, fb->info.var.xres, fb->info.var.yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) FINISH_ATTR_ACCESS(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rattlerSetupPlanes(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int saved_id, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Write RAMDAC pixel read mask register so all overlay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * planes are display-enabled. (CRX24 uses Bt462 pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * read mask register for overlay planes, not image planes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) CRX24_SETUP_RAMDAC(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* change fb->id temporarily to fool SETUP_FB() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) saved_id = fb->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fb->id = CRX24_OVERLAY_PLANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) fb->id = saved_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (y = 0; y < fb->info.var.yres; ++y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fb_memset(fb->info.screen_base + y * fb->info.fix.line_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0xff, fb->info.var.xres * fb->info.var.bits_per_pixel/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CRX24_SET_OVLY_MASK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define HYPER_CMAP_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define NGLE_CMAP_INDEXED0_TYPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define NGLE_CMAP_OVERLAY_TYPE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* typedef of LUT (Colormap) BLT Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) typedef union /* Note assumption that fields are packed left-to-right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { u32 all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned enable : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned waitBlank : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned reserved1 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned lutOffset : 10; /* Within destination LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned lutType : 2; /* Cursor, image, overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned reserved2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned length : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } NgleLutBltCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static NgleLutBltCtl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) setNgleLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) NgleLutBltCtl lutBltCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* set enable, zero reserved fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) lutBltCtl.all = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) lutBltCtl.fields.length = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) switch (fb->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case S9000_ID_A1439A: /* CRX24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (fb->var.bits_per_pixel == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) lutBltCtl.fields.lutType = NGLE_CMAP_OVERLAY_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) lutBltCtl.fields.lutOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) lutBltCtl.fields.lutOffset = 0 * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case S9000_ID_ARTIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) lutBltCtl.fields.lutOffset = 0 * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) lutBltCtl.fields.lutOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Offset points to start of LUT. Adjust for within LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) lutBltCtl.fields.lutOffset += offsetWithinLut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return lutBltCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static NgleLutBltCtl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) setHyperLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) NgleLutBltCtl lutBltCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* set enable, zero reserved fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) lutBltCtl.all = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) lutBltCtl.fields.length = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) lutBltCtl.fields.lutType = HYPER_CMAP_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Expect lutIndex to be 0 or 1 for image cmaps, 2 or 3 for overlay cmaps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (fb->info.var.bits_per_pixel == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) lutBltCtl.fields.lutOffset = 2 * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) lutBltCtl.fields.lutOffset = 0 * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Offset points to start of LUT. Adjust for within LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) lutBltCtl.fields.lutOffset += offsetWithinLut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return lutBltCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void hyperUndoITE(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int nFreeFifoSlots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 fbAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) NGLE_LOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) WRITE_WORD(0xffffffff, fb, REG_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Write overlay transparency mask so only entry 255 is transparent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Hardware setup for full-depth write to "magic" location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) NGLE_QUICK_SET_DST_BM_ACCESS(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) BA(IndexedDcd, Otc04, Ots08, AddrLong,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) BAJustPoint(0), BINovly, BAIndexBase(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) IBOvals(RopSrc, MaskAddrOffset(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) BitmapExtent08, StaticReg(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DataDynamic, MaskOtc, BGx(0), FGx(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Now prepare to write to the "magic" location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) fbAddr = NGLE_LONG_FB_ADDRESS(0, 1532, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) NGLE_BINC_SET_DSTADDR(fb, fbAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) NGLE_BINC_SET_DSTMASK(fb, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Finally, write a zero to clear the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) NGLE_BINC_WRITE32(fb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) NGLE_UNLOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ngleDepth8_ClearImagePlanes(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* FIXME! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ngleDepth24_ClearImagePlanes(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* FIXME! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ngleResetAttrPlanes(struct stifb_info *fb, unsigned int ctlPlaneReg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int nFreeFifoSlots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 packed_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 packed_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) NGLE_LOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) NGLE_QUICK_SET_DST_BM_ACCESS(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) BA(IndexedDcd, Otc32, OtsIndirect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) AddrLong, BAJustPoint(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) BINattr, BAIndexBase(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) NGLE_QUICK_SET_CTL_PLN_REG(fb, ctlPlaneReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) NGLE_SET_TRANSFERDATA(fb, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) IBOvals(RopSrc, MaskAddrOffset(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) BitmapExtent08, StaticReg(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) DataDynamic, MaskOtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) BGx(0), FGx(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) packed_dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) NGLE_SET_DSTXY(fb, packed_dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SET_LENXY_START_RECFILL(fb, packed_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * In order to work around an ELK hardware problem (Buffy doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * always flush it's buffers when writing to the attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * planes), at least 4 pixels must be written to the attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * planes starting at (X == 1280) and (Y != to the last Y written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * by BIF):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (fb->id == S9000_ID_A1659A) { /* ELK_DEVICE_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* It's safe to use scanline zero: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) packed_dst = (1280 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) NGLE_SET_DSTXY(fb, packed_dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) packed_len = (4 << 16) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) SET_LENXY_START_RECFILL(fb, packed_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) } /* ELK Hardware Kludge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /**** Finally, set the Control Plane Register back to zero: ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) NGLE_QUICK_SET_CTL_PLN_REG(fb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) NGLE_UNLOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ngleClearOverlayPlanes(struct stifb_info *fb, int mask, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int nFreeFifoSlots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 packed_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 packed_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) NGLE_LOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Hardware setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) NGLE_QUICK_SET_DST_BM_ACCESS(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) BA(IndexedDcd, Otc04, Ots08, AddrLong,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) BAJustPoint(0), BINovly, BAIndexBase(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) NGLE_SET_TRANSFERDATA(fb, 0xffffffff); /* Write foreground color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) packed_dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) NGLE_SET_DSTXY(fb, packed_dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Write zeroes to overlay planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) IBOvals(RopSrc, MaskAddrOffset(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) BitmapExtent08, StaticReg(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DataDynamic, MaskOtc, BGx(0), FGx(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SET_LENXY_START_RECFILL(fb, packed_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) NGLE_UNLOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) hyperResetPlanes(struct stifb_info *fb, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) unsigned int controlPlaneReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) NGLE_LOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (IS_24_DEVICE(fb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (fb->info.var.bits_per_pixel == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) controlPlaneReg = 0x04000F00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) controlPlaneReg = 0x00000F00; /* 0x00000800 should be enough, but lets clear all 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) controlPlaneReg = 0x00000F00; /* 0x00000100 should be enough, but lets clear all 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) switch (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* clear screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (IS_24_DEVICE(fb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ngleDepth24_ClearImagePlanes(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ngleDepth8_ClearImagePlanes(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Paint attribute planes for default case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * On Hyperdrive, this means all windows using overlay cmap 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ngleResetAttrPlanes(fb, controlPlaneReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* clear overlay planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ngleClearOverlayPlanes(fb, 0xff, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ** Also need to counteract ITE settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) hyperUndoITE(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* clear screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (IS_24_DEVICE(fb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ngleDepth24_ClearImagePlanes(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ngleDepth8_ClearImagePlanes(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ngleResetAttrPlanes(fb, controlPlaneReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ngleClearOverlayPlanes(fb, 0xff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case -1: /* RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) hyperUndoITE(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ngleResetAttrPlanes(fb, controlPlaneReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) NGLE_UNLOCK(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Return pointer to in-memory structure holding ELK device-dependent ROM values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ngleGetDeviceRomData(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) XXX: FIXME: !!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int *pBytePerLongDevDepData;/* data byte == LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int *pRomTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) NgleDevRomData *pPackedDevRomData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int sizePackedDevRomData = sizeof(*pPackedDevRomData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) char *pCard8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) char *mapOrigin = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int romTableIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pPackedDevRomData = fb->ngle_rom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (fb->id == S9000_ID_ARTIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) pPackedDevRomData->cursor_pipeline_delay = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pPackedDevRomData->video_interleaves = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Get pointer to unpacked byte/long data in ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pBytePerLongDevDepData = fb->sti->regions[NGLEDEVDEPROM_CRT_REGION];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Tomcat supports several resolutions: 1280x1024, 1024x768, 640x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (fb->id == S9000_ID_TOMCAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* jump to the correct ROM table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GET_ROMTABLE_INDEX(romTableIdx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) while (romTableIdx > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pCard8 = (Card8 *) pPackedDevRomData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pRomTable = pBytePerLongDevDepData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Pack every fourth byte from ROM into structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (i = 0; i < sizePackedDevRomData; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *pCard8++ = (Card8) (*pRomTable++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pBytePerLongDevDepData = (Card32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ((Card8 *) pBytePerLongDevDepData +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pPackedDevRomData->sizeof_ngle_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) romTableIdx--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pCard8 = (Card8 *) pPackedDevRomData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Pack every fourth byte from ROM into structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) for (i = 0; i < sizePackedDevRomData; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) *pCard8++ = (Card8) (*pBytePerLongDevDepData++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define HYPERBOWL_MODE2_8_24 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* HCRX specific boot-time initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SETUP_HCRX(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int hyperbowl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int nFreeFifoSlots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (fb->id != S9000_ID_HCRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* Initialize Hyperbowl registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (IS_24_DEVICE(fb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) hyperbowl = (fb->info.var.bits_per_pixel == 32) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* First write to Hyperbowl must happen twice (bug) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) WRITE_WORD(hyperbowl, fb, REG_40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) WRITE_WORD(hyperbowl, fb, REG_40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) WRITE_WORD(HYPERBOWL_MODE2_8_24, fb, REG_39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) WRITE_WORD(0x014c0148, fb, REG_42); /* Set lut 0 to be the direct color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) WRITE_WORD(0x404c4048, fb, REG_43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) WRITE_WORD(0x034c0348, fb, REG_44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) WRITE_WORD(0x444c4448, fb, REG_45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) hyperbowl = HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* First write to Hyperbowl must happen twice (bug) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) WRITE_WORD(hyperbowl, fb, REG_40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) WRITE_WORD(hyperbowl, fb, REG_40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) WRITE_WORD(0x00000000, fb, REG_42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) WRITE_WORD(0x00000000, fb, REG_43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) WRITE_WORD(0x00000000, fb, REG_44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) WRITE_WORD(0x444c4048, fb, REG_45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* ------------------- driver specific functions --------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) stifb_setcolreg(u_int regno, u_int red, u_int green,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u_int blue, u_int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct stifb_info *fb = container_of(info, struct stifb_info, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u32 color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (regno >= NR_PALETTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) red >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) green >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) blue >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) DEBUG_OFF();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) START_IMAGE_COLORMAP_ACCESS(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (unlikely(fb->info.var.grayscale)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* gray = 0.30*R + 0.59*G + 0.11*B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) color = ((red * 77) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) (green * 151) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) (blue * 28)) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) color = ((red << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (green << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) (blue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (fb->info.fix.visual == FB_VISUAL_DIRECTCOLOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct fb_var_screeninfo *var = &fb->info.var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (regno < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ((u32 *)fb->info.pseudo_palette)[regno] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) regno << var->red.offset |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) regno << var->green.offset |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) regno << var->blue.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) WRITE_IMAGE_COLOR(fb, regno, color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (fb->id == S9000_ID_HCRX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) NgleLutBltCtl lutBltCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) lutBltCtl = setHyperLutBltCtl(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) 0, /* Offset w/i LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) 256); /* Load entire LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) NGLE_BINC_SET_SRCADDR(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) NGLE_LONG_FB_ADDRESS(0, 0x100, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* 0x100 is same as used in WRITE_IMAGE_COLOR() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) START_COLORMAPLOAD(fb, lutBltCtl.all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* cleanup colormap hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) FINISH_IMAGE_COLORMAP_ACCESS(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) DEBUG_ON();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) stifb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct stifb_info *fb = container_of(info, struct stifb_info, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int enable = (blank_mode == 0) ? ENABLE : DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) switch (fb->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case S9000_ID_A1439A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) CRX24_ENABLE_DISABLE_DISPLAY(fb, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case CRT_ID_VISUALIZE_EG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case S9000_ID_ARTIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ARTIST_ENABLE_DISABLE_DISPLAY(fb, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) case S9000_ID_HCRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) HYPER_ENABLE_DISABLE_DISPLAY(fb, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case S9000_ID_A1659A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case S9000_ID_TIMBER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) case CRX24_OVERLAY_PLANES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ENABLE_DISABLE_DISPLAY(fb, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) stifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct stifb_info *fb = container_of(info, struct stifb_info, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) SETUP_COPYAREA(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (fb->info.var.bits_per_pixel == 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) WRITE_WORD(0xBBA0A000, fb, REG_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) WRITE_WORD(fb->id == S9000_ID_HCRX ? 0x13a02000 : 0x13a01000, fb, REG_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) IBOvals(RopSrc, MaskAddrOffset(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) BitmapExtent08, StaticReg(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) DataDynamic, MaskOtc, BGx(0), FGx(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) WRITE_WORD(((area->sx << 16) | area->sy), fb, REG_24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) WRITE_WORD(((area->width << 16) | area->height), fb, REG_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) WRITE_WORD(((area->dx << 16) | area->dy), fb, REG_25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) stifb_init_display(struct stifb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int id = fb->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* HCRX specific initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SETUP_HCRX(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (id == S9000_ID_HCRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) hyperInitSprite(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ngleInitSprite(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Initialize the image planes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) case S9000_ID_HCRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) hyperResetPlanes(fb, ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case S9000_ID_A1439A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) rattlerSetupPlanes(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) case S9000_ID_A1659A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) case S9000_ID_ARTIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case CRT_ID_VISUALIZE_EG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) elkSetupPlanes(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Clear attribute planes on non HCRX devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case S9000_ID_A1659A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case S9000_ID_A1439A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (fb->info.var.bits_per_pixel == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ngleSetupAttrPlanes(fb, BUFF1_CMAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (id == S9000_ID_A1439A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ngleClearOverlayPlanes(fb, 0xff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case S9000_ID_ARTIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case CRT_ID_VISUALIZE_EG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (fb->info.var.bits_per_pixel == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ngleSetupAttrPlanes(fb, ARTIST_CMAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) stifb_blank(0, (struct fb_info *)fb); /* 0=enable screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SETUP_FB(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* ------------ Interfaces to hardware functions ------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct fb_ops stifb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .fb_setcolreg = stifb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .fb_blank = stifb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .fb_copyarea = stifb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct fb_fix_screeninfo *fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct fb_var_screeninfo *var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct stifb_info *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) unsigned long sti_rom_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) char *dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int bpp, xres, yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) fb = kzalloc(sizeof(*fb), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (!fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) info = &fb->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* set struct to a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) fix = &info->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) fb->sti = sti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_name = sti->sti_data->inq_outptr.dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* store upper 32bits of the graphics id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) fb->id = fb->sti->graphics_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* only supported cards are allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) switch (fb->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case CRT_ID_VISUALIZE_EG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* Visualize cards can run either in "double buffer" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "standard" mode. Depending on the mode, the card reports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) a different device name, e.g. "INTERNAL_EG_DX1024" in double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) buffer mode and "INTERNAL_EG_X1024" in standard mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) Since this driver only supports standard mode, we check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if the device name contains the string "DX" and tell the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) user how to reconfigure the card. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (strstr(dev_name, "DX")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "WARNING: stifb framebuffer driver does not support '%s' in double-buffer mode.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) "WARNING: Please disable the double-buffer mode in IPL menu (the PARISC-BIOS).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) goto out_err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) case S9000_ID_ARTIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) case S9000_ID_HCRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case S9000_ID_TIMBER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) case S9000_ID_A1659A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case S9000_ID_A1439A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) printk(KERN_WARNING "stifb: '%s' (id: 0x%08x) not supported.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev_name, fb->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto out_err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* default to 8 bpp on most graphic chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) bpp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) xres = sti_onscreen_x(fb->sti);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) yres = sti_onscreen_y(fb->sti);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ngleGetDeviceRomData(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* get (virtual) io region base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) fix->mmio_start = REGION_BASE(fb,2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) fix->mmio_len = 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Reject any device not in the NGLE family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) switch (fb->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case S9000_ID_A1659A: /* CRX/A1659A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case S9000_ID_ELM: /* GRX, grayscale but else same as A1659A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) var->grayscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) fb->id = S9000_ID_A1659A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) case S9000_ID_TIMBER: /* HP9000/710 Any (may be a grayscale device) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (strstr(dev_name, "GRAYSCALE") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) strstr(dev_name, "Grayscale") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) strstr(dev_name, "grayscale"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) var->grayscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) case S9000_ID_TOMCAT: /* Dual CRX, behaves else like a CRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* FIXME: TomCat supports two heads:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * fb.iobase = REGION_BASE(fb_info,3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * fb.screen_base = ioremap(REGION_BASE(fb_info,2),xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * for now we only support the left one ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) xres = fb->ngle_rom.x_size_visible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) yres = fb->ngle_rom.y_size_visible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) fb->id = S9000_ID_A1659A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) case S9000_ID_A1439A: /* CRX24/A1439A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bpp = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case S9000_ID_HCRX: /* Hyperdrive/HCRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) memset(&fb->ngle_rom, 0, sizeof(fb->ngle_rom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if ((fb->sti->regions_phys[0] & 0xfc000000) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) (fb->sti->regions_phys[2] & 0xfc000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sti_rom_address = F_EXTEND(fb->sti->regions_phys[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) sti_rom_address = F_EXTEND(fb->sti->regions_phys[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) fb->deviceSpecificConfig = gsc_readl(sti_rom_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (IS_24_DEVICE(fb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (bpp_pref == 8 || bpp_pref == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) bpp = bpp_pref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bpp = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) bpp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) READ_WORD(fb, REG_15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SETUP_HW(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case CRT_ID_VISUALIZE_EG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case S9000_ID_ARTIST: /* Artist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #ifdef FALLBACK_TO_1BPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "stifb: Unsupported graphics card (id=0x%08x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "- now trying 1bpp mode instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) fb->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) bpp = 1; /* default to 1 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "stifb: Unsupported graphics card (id=0x%08x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "- skipping.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) fb->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) goto out_err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* get framebuffer physical and virtual base addr & len (64bit ready) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) fix->smem_start = F_EXTEND(fb->sti->regions_phys[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) fix->smem_len = fb->sti->regions[1].region_desc.length * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) fix->line_length = (fb->sti->glob_cfg->total_x * bpp) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (!fix->line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) fix->line_length = 2048; /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* limit fbsize to max visible screen size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (fix->smem_len > yres*fix->line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) fix->smem_len = yres*fix->line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) fix->accel = FB_ACCEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) switch (bpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) fix->type = FB_TYPE_PLANES; /* well, sort of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) fix->visual = FB_VISUAL_MONO10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) var->red.length = var->green.length = var->blue.length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) fix->type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) fix->visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) var->red.length = var->green.length = var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) fix->type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) fix->visual = FB_VISUAL_DIRECTCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) var->red.length = var->green.length = var->blue.length = var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) var->green.offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) var->red.offset = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) var->transp.offset = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) var->xres = var->xres_virtual = xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) var->yres = var->yres_virtual = yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) var->bits_per_pixel = bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) strcpy(fix->id, "stifb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) info->fbops = &stifb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) info->screen_base = ioremap(REGION_BASE(fb,1), fix->smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) printk(KERN_ERR "stifb: failed to map memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) goto out_err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) info->screen_size = fix->smem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) info->pseudo_palette = &fb->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* This has to be done !!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto out_err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) stifb_init_display(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (!request_mem_region(fix->smem_start, fix->smem_len, "stifb fb")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) printk(KERN_ERR "stifb: cannot reserve fb region 0x%04lx-0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) fix->smem_start, fix->smem_start+fix->smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) goto out_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!request_mem_region(fix->mmio_start, fix->mmio_len, "stifb mmio")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) printk(KERN_ERR "stifb: cannot reserve sti mmio region 0x%04lx-0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) fix->mmio_start, fix->mmio_start+fix->mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) goto out_err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (register_framebuffer(&fb->info) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) goto out_err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) sti->info = info; /* save for unregister_framebuffer() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) fb_info(&fb->info, "%s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) fix->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) var->xres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) var->yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) var->bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) fb->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) fix->mmio_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) out_err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) release_mem_region(fix->mmio_start, fix->mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) out_err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) release_mem_region(fix->smem_start, fix->smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) out_err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) out_err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) out_err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) kfree(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int stifb_disabled __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) stifb_setup(char *options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static int __init stifb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct sti_struct *sti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct sti_struct *def_sti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (fb_get_options("stifb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) stifb_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (stifb_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) printk(KERN_INFO "stifb: disabled by \"stifb=off\" kernel parameter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) def_sti = sti_get_rom(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (def_sti) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) for (i = 1; i <= MAX_STI_ROMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) sti = sti_get_rom(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!sti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (sti == def_sti) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) stifb_init_fb(sti, stifb_bpp_pref[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) for (i = 1; i <= MAX_STI_ROMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) sti = sti_get_rom(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!sti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (sti == def_sti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) stifb_init_fb(sti, stifb_bpp_pref[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) stifb_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct sti_struct *sti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) for (i = 1; i <= MAX_STI_ROMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) sti = sti_get_rom(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!sti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (sti->info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct fb_info *info = sti->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) unregister_framebuffer(sti->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) release_mem_region(info->fix.smem_start, info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) sti->info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) stifb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (strncmp(options, "off", 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) stifb_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) options += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (strncmp(options, "bpp", 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) options += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) for (i = 0; i < MAX_STI_ROMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (*options++ != ':')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) stifb_bpp_pref[i] = simple_strtoul(options, &options, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) __setup("stifb=", stifb_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) module_init(stifb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) module_exit(stifb_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) MODULE_AUTHOR("Helge Deller <deller@gmx.de>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) MODULE_DESCRIPTION("Framebuffer driver for HP's NGLE series graphics cards in HP PARISC machines");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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