^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Silicon Motion SM712 frame buffer device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006 Silicon Motion Technology Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Ge Wang, gewang@siliconmotion.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Boyod boyod.yang@siliconmotion.com.cn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 Lemote, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Wu Zhangjin, wuzhangjin@gmail.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FB_ACCEL_SMI_LYNX 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SCREEN_X_RES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SCREEN_Y_RES_PC 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCREEN_Y_RES_NETBOOK 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCREEN_BPP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define dac_reg (0x3c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define dac_val (0x3c9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern void __iomem *smtc_regbaseaddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline void smtc_crtcw(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) smtc_mmiowb(reg, 0x3d4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) smtc_mmiowb(val, 0x3d5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void smtc_grphw(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) smtc_mmiowb(reg, 0x3ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) smtc_mmiowb(val, 0x3cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline void smtc_attrw(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) smtc_mmiorb(0x3da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) smtc_mmiowb(reg, 0x3c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) smtc_mmiorb(0x3c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) smtc_mmiowb(val, 0x3c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void smtc_seqw(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) smtc_mmiowb(reg, 0x3c4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) smtc_mmiowb(val, 0x3c5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline unsigned int smtc_seqr(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) smtc_mmiowb(reg, 0x3c4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return smtc_mmiorb(0x3c5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* The next structure holds all information relevant for a specific video mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct modeinit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int mmsizex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int mmsizey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned char init_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned char init_sr00_sr04[SIZE_SR00_SR04];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned char init_sr10_sr24[SIZE_SR10_SR24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char init_sr30_sr75[SIZE_SR30_SR75];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char init_sr80_sr93[SIZE_SR80_SR93];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned char init_gr00_gr08[SIZE_GR00_GR08];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned char init_ar00_ar14[SIZE_AR00_AR14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned char init_cr00_cr18[SIZE_CR00_CR18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned char init_cr90_cra7[SIZE_CR90_CRA7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ((g & 0xe000) >> 13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ((g & 0x1c00) << 3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ((b & 0xf800) >> 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define big_addr 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define mmio_addr 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define seqw17() smtc_seqw(0x17, 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define big_swap(p) ((p & 0xff00ff00 >> 8) | (p & 0x00ff00ff << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define pal_rgb(r, g, b, val) val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define big_addr 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define mmio_addr 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define seqw17() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define big_pixel_depth(p, d) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define big_swap(p) p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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