^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SH7760/SH7763 LCDC Framebuffer driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Manuel Lauss <mano@roarinelk.homelinux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * PLEASE HAVE A LOOK AT Documentation/fb/sh7760fb.rst!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * for his original source and testing!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * sh7760_setcolreg get from drivers/video/sh_mobile_lcdcfb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/sh7760fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct sh7760fb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sh7760fb_platdata *pd; /* display information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) dma_addr_t fbdma; /* physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int rot; /* rotation enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct platform_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct resource *ioarea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct completion vsync; /* vsync irq event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static irqreturn_t sh7760fb_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct completion *c = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) complete(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* wait_for_lps - wait until power supply has reached a certain state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int wait_for_lps(struct sh7760fb_par *par, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) while (--i && ((ioread16(par->base + LDPMMR) & 3) != val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (i <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* en/disable the LCDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int sh7760fb_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sh7760fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct sh7760fb_platdata *pd = par->pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned short cntr = ioread16(par->base + LDCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned short intr = ioread16(par->base + LDINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int lps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (blank == FB_BLANK_UNBLANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) intr |= VINT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cntr = LDCNTR_DON2 | LDCNTR_DON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) lps = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) intr &= ~VINT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) cntr = LDCNTR_DON2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) lps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (pd->blank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pd->blank(blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) iowrite16(intr, par->base + LDINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) iowrite16(cntr, par->base + LDCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return wait_for_lps(par, lps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int sh7760_setcolreg (u_int regno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u_int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 *palette = info->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (regno >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* only FB_VISUAL_TRUECOLOR supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) red >>= 16 - info->var.red.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) green >>= 16 - info->var.green.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) blue >>= 16 - info->var.blue.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) transp >>= 16 - info->var.transp.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) palette[regno] = (red << info->var.red.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (green << info->var.green.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (blue << info->var.blue.offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (transp << info->var.transp.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int sh7760fb_get_color_info(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 lddfr, int *bpp, int *gray)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int lbpp, lgray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) lgray = lbpp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (lddfr & LDDFR_COLOR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case LDDFR_1BPP_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) lgray = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) lbpp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case LDDFR_2BPP_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) lgray = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) lbpp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case LDDFR_4BPP_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) lgray = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case LDDFR_4BPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) lbpp = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case LDDFR_6BPP_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) lgray = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case LDDFR_8BPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) lbpp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case LDDFR_16BPP_RGB555:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case LDDFR_16BPP_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) lbpp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) lgray = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_dbg(dev, "unsupported LDDFR bit depth.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *bpp = lbpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (gray)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *gray = lgray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int sh7760fb_check_var(struct fb_var_screeninfo *var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct fb_fix_screeninfo *fix = &info->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct sh7760fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret, bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* get color info from register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) var->bits_per_pixel = bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if ((var->grayscale) && (var->bits_per_pixel == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) fix->visual = FB_VISUAL_MONO10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else if (var->bits_per_pixel >= 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) fix->visual = FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) fix->visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* TODO: add some more validation here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * sh7760fb_set_par - set videomode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * NOTE: The rotation, grayscale and DSTN codepaths are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * totally untested!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int sh7760fb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct sh7760fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct fb_videomode *vm = par->pd->def_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long sbase, dstn_off, ldsarl, stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned short hsynp, hsynw, htcn, hdcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned short vsynp, vsynw, vtln, vdln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned short lddfr, ldmtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ret, bpp, gray;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) par->rot = par->pd->rotate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* rotate only works with xres <= 320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (par->rot && (vm->xres > 320)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_dbg(info->dev, "rotation disabled due to display size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) par->rot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* calculate LCDC reg vals from display parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) hsynp = vm->right_margin + vm->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) hsynw = vm->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) htcn = vm->left_margin + hsynp + hsynw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) hdcn = vm->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) vsynp = vm->lower_margin + vm->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) vsynw = vm->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) vtln = vm->upper_margin + vsynp + vsynw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) vdln = vm->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* get color info from register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, &gray);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(info->dev, "%dx%d %dbpp %s (orientation %s)\n", hdcn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vdln, bpp, gray ? "grayscale" : "color",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) par->rot ? "rotated" : "normal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) lddfr = par->pd->lddfr | (1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) lddfr = par->pd->lddfr & ~(1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ldmtr = par->pd->ldmtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!(vm->sync & FB_SYNC_HOR_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ldmtr |= LDMTR_CL1POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!(vm->sync & FB_SYNC_VERT_HIGH_ACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ldmtr |= LDMTR_FLMPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* shut down LCDC before changing display parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sh7760fb_blank(FB_BLANK_POWERDOWN, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) iowrite16(par->pd->ldickr, par->base + LDICKR); /* pixclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) iowrite16(ldmtr, par->base + LDMTR); /* polarities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) iowrite16(lddfr, par->base + LDDFR); /* color/depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) iowrite16((par->rot ? 1 << 13 : 0), par->base + LDSMR); /* rotate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) iowrite16(par->pd->ldpmmr, par->base + LDPMMR); /* Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) iowrite16(par->pd->ldpspr, par->base + LDPSPR); /* Power Supply Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* display resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) iowrite16(((htcn >> 3) - 1) | (((hdcn >> 3) - 1) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) par->base + LDHCNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) iowrite16(vdln - 1, par->base + LDVDLNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) iowrite16(vtln - 1, par->base + LDVTLNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* h/v sync signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) iowrite16((vsynp - 1) | ((vsynw - 1) << 12), par->base + LDVSYNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) iowrite16(((hsynp >> 3) - 1) | (((hsynw >> 3) - 1) << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) par->base + LDHSYNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* AC modulation sig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) iowrite16(par->pd->ldaclnr, par->base + LDACLNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) stride = (par->rot) ? vtln : hdcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!gray)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) stride *= (bpp + 7) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (bpp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) stride >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else if (bpp == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) stride >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else if (bpp == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) stride >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* 6 bpp == 8 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* if rotated, stride must be power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (par->rot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long bit = 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) while (bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (stride & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bit >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (stride & ~bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) stride = bit << 1; /* not P-o-2, round up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) iowrite16(stride, par->base + LDLAOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* set display mem start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sbase = (unsigned long)par->fbdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (par->rot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sbase += (hdcn - 1) * stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) iowrite32(sbase, par->base + LDSARU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * for DSTN need to set address for lower half.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * I (mlau) don't know which address to set it to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * so I guessed at (stride * yres/2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (((ldmtr & 0x003f) >= LDMTR_DSTN_MONO_8) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ((ldmtr & 0x003f) <= LDMTR_DSTN_COLOR_16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_dbg(info->dev, " ***** DSTN untested! *****\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dstn_off = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (par->rot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dstn_off *= hdcn >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dstn_off *= vdln >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ldsarl = sbase + dstn_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ldsarl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) iowrite32(ldsarl, par->base + LDSARL); /* mem for lower half of DSTN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) info->fix.line_length = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sh7760fb_check_var(&info->var, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sh7760fb_blank(FB_BLANK_UNBLANK, info); /* panel on! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(info->dev, "hdcn : %6d htcn : %6d\n", hdcn, htcn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_dbg(info->dev, "hsynw : %6d hsynp : %6d\n", hsynw, hsynp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(info->dev, "vdln : %6d vtln : %6d\n", vdln, vtln);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_dbg(info->dev, "vsynw : %6d vsynp : %6d\n", vsynw, vsynp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_dbg(info->dev, "clksrc: %6d clkdiv: %6d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (par->pd->ldickr >> 12) & 3, par->pd->ldickr & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_dbg(info->dev, "ldpmmr: 0x%04x ldpspr: 0x%04x\n", par->pd->ldpmmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) par->pd->ldpspr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(info->dev, "ldmtr : 0x%04x lddfr : 0x%04x\n", ldmtr, lddfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_dbg(info->dev, "ldlaor: %ld\n", stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(info->dev, "ldsaru: 0x%08lx ldsarl: 0x%08lx\n", sbase, ldsarl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct fb_ops sh7760fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .fb_blank = sh7760fb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .fb_check_var = sh7760fb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .fb_setcolreg = sh7760_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .fb_set_par = sh7760fb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void sh7760fb_free_mem(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct sh7760fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dma_free_coherent(info->dev, info->screen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) info->screen_base, par->fbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) par->fbdma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) info->screen_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) info->screen_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* allocate the framebuffer memory. This memory must be in Area3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * (dictated by the DMA engine) and contiguous, at a 512 byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int sh7760fb_alloc_mem(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct sh7760fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void *fbmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret, bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* get color info from register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) printk(KERN_ERR "colinfo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* min VRAM: xres_min = 16, yres_min = 1, bpp = 1: 2byte -> 1 page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) max VRAM: xres_max = 1024, yres_max = 1024, bpp = 16: 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) vram = info->var.xres * info->var.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (info->var.grayscale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (bpp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) vram >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else if (bpp == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) vram >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else if (bpp == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) vram >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else if (bpp > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) vram *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if ((vram < 1) || (vram > 1024 * 2048)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_dbg(info->dev, "too much VRAM required. Check settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (vram < PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) vram = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) fbmem = dma_alloc_coherent(info->dev, vram, &par->fbdma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!fbmem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if ((par->fbdma & SH7760FB_DMA_MASK) != SH7760FB_DMA_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) sh7760fb_free_mem(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(info->dev, "kernel gave me memory at 0x%08lx, which is"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "unusable for the LCDC\n", (unsigned long)par->fbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) info->screen_base = fbmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) info->screen_size = vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) info->fix.smem_start = (unsigned long)info->screen_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) info->fix.smem_len = info->screen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int sh7760fb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct sh7760fb_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (unlikely(res == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(&pdev->dev, "invalid resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) info = framebuffer_alloc(sizeof(struct sh7760fb_par), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) par->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) par->pd = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!par->pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_dbg(info->dev, "no display setup data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto out_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) par->ioarea = request_mem_region(res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) resource_size(res), pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!par->ioarea) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&pdev->dev, "mmio area busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto out_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) par->base = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!par->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(&pdev->dev, "cannot remap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto out_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) iowrite16(0, par->base + LDINTR); /* disable vsync irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) par->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (par->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = request_irq(par->irq, sh7760fb_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "sh7760-lcdc", &par->vsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(&pdev->dev, "cannot grab IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) par->irq = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) disable_irq_nosync(par->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fb_videomode_to_var(&info->var, par->pd->def_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = sh7760fb_alloc_mem(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(info->dev, "framebuffer memory allocation failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) info->pseudo_palette = par->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* fixup color register bitpositions. These are fixed by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) info->var.red.offset = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) info->var.red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) info->var.red.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) info->var.green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) info->var.green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) info->var.green.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) info->var.blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) info->var.blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) info->var.blue.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) info->var.transp.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) info->var.transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) info->var.transp.msb_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) strcpy(info->fix.id, "sh7760-lcdc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* set the DON2 bit now, before cmap allocation, as it will randomize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * palette memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) iowrite16(LDCNTR_DON2, par->base + LDCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) info->fbops = &sh7760fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_dbg(info->dev, "Unable to allocate cmap memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto out_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = register_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_dbg(info->dev, "cannot register fb!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto out_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) printk(KERN_INFO "%s: memory at phys 0x%08lx-0x%08lx, size %ld KiB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) (unsigned long)par->fbdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (unsigned long)(par->fbdma + info->screen_size - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) info->screen_size >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) out_cmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sh7760fb_blank(FB_BLANK_POWERDOWN, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) out_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sh7760fb_free_mem(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (par->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) free_irq(par->irq, &par->vsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) iounmap(par->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) out_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) out_fb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int sh7760fb_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct fb_info *info = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct sh7760fb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sh7760fb_blank(FB_BLANK_POWERDOWN, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sh7760fb_free_mem(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (par->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) free_irq(par->irq, &par->vsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) iounmap(par->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) release_mem_region(par->ioarea->start, resource_size(par->ioarea));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct platform_driver sh7760_lcdc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "sh7760-lcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .probe = sh7760fb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .remove = sh7760fb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) module_platform_driver(sh7760_lcdc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MODULE_AUTHOR("Nobuhiro Iwamatsu, Manuel Lauss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MODULE_DESCRIPTION("FBdev for SH7760/63 integrated LCD Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags