^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Public License. See the file COPYING in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SAVAGEFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SAVAGEFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../edid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef SAVAGEFB_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define DBG(x) no_printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) # define SavagePrintRegs(...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_CHIP_SAVAGE4 0x8a22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_CHIP_SAVAGE3D 0x8a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_CHIP_SAVAGE3D_MV 0x8a21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_CHIP_SAVAGE2000 0x9102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCI_CHIP_SAVAGE_MX 0x8c11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_CHIP_SAVAGE_IX 0x8c13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_CHIP_PROSAVAGE_PM 0x8a25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI_CHIP_PROSAVAGE_KM 0x8a26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_CHIP_S3TWISTER_P 0x8d01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_CHIP_S3TWISTER_K 0x8d02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_CHIP_SUPSAV_MX128 0x8c22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_CHIP_SUPSAV_MX64 0x8c24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_CHIP_SUPSAV_MX64C 0x8c26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Chip tags. These are used to group the adapters into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * related families.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) S3_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) S3_SAVAGE3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) S3_SAVAGE_MX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) S3_SAVAGE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) S3_PROSAVAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) S3_TWISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) S3_PROSAVAGEDDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) S3_SUPERSAVAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) S3_SAVAGE2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) S3_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } savage_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BIOS_BSIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BIOS_BASE 0xc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAVAGE_NEWMMIO_VGABASE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BASE_FREQ 14318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HALF_BASE_FREQ 7159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FIFO_CONTROL_REG 0x8200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MIU_CONTROL_REG 0x8204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STREAMS_TIMEOUT_REG 0x8208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MISC_TIMEOUT_REG 0x820c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MONO_PAT_0 0xa4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MONO_PAT_1 0xa4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAXFIFO 0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BCI_CMD_NOP 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BCI_CMD_SETREG 0x96000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BCI_CMD_RECT 0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BCI_CMD_RECT_XP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BCI_CMD_RECT_YP 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BCI_CMD_SEND_COLOR 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BCI_CMD_DEST_GBD 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCI_CMD_SRC_GBD 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BCI_CMD_SRC_SOLID 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BCI_CMD_SRC_MONO 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BCI_CMD_CLIP_NEW 0x00006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BCI_CMD_CLIP_LR 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BCI_GBD1 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BCI_GBD2 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BCI_BUFFER_OFFSET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BCI_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BCI_CMD_SEND_COLOR 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DISP_CRT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DISP_LCD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DISP_DFP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct xtimings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int Clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int HDisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int HSyncStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int HSyncEnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int HTotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int HAdjusted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int VDisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int VSyncStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int VSyncEnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int VTotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int dblscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int interlaced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct savage_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned char MiscOutReg; /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned char CRTC[25]; /* Crtc Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned char Sequencer[5]; /* Video Sequencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned char Graphics[9]; /* Video Graphics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned char Attribute[21]; /* Video Attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int mode, refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char SR08, SR0E, SR0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char SR54[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned char Clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned char CR40, CR41, CR42, CR43, CR45;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned char CR86, CR88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned char CR90, CR91, CRB0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int STREAMS[22]; /* yuck, streams regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NR_PALETTE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct savagefb_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct savagefb_i2c_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct savagefb_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct i2c_algo_bit_data algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) volatile u8 __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct savagefb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct pci_dev *pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) savage_chipset chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct savagefb_i2c_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct savage_reg state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct savage_reg save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct savage_reg initial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct vgastate vgastate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mutex open_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned char *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 open_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int paletteEnabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int pm_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int display_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int dvi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int crtonly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int dacSpeedBpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int maxClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int minClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int numClocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int clock[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int MCLK, REFCLK, LCDclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 pbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) volatile u32 __iomem *bci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int bci_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 cob_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 cob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int cob_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void (*SavageWaitIdle) (struct savagefb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void (*SavageWaitFifo) (struct savagefb_par *par, int space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int HorizScaleFactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Panels size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int SavagePanelWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int SavagePanelHeight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u16 red, green, blue, transp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } palette[NR_PALETTE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int vwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define BCI_BD_BW_DISABLE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* IO functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return readb(par->mmio.vbase + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return readw(par->mmio.vbase + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return readl(par->mmio.vbase + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writeb(val, par->mmio.vbase + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writew(val, par->mmio.vbase + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel(val, par->mmio.vbase + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline u8 vga_in8(int addr, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return savage_in8(0x8000 + addr, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline u16 vga_in16(int addr, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return savage_in16(0x8000 + addr, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline u8 vga_in32(int addr, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return savage_in32(0x8000 + addr, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) savage_out8(0x8000 + addr, val, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) savage_out16(0x8000 + addr, val, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) savage_out32(0x8000 + addr, val, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline u8 VGArCR (u8 index, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) vga_out8(0x3d4, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return vga_in8(0x3d5, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static inline u8 VGArGR (u8 index, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) vga_out8(0x3ce, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return vga_in8(0x3cf, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) vga_out8(0x3c4, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return vga_in8(0x3c5, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) vga_out8(0x3d4, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) vga_out8(0x3d5, val, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) vga_out8(0x3ce, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vga_out8(0x3cf, val, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vga_out8(0x3c4, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) vga_out8 (0x3c5, val, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline void VGAenablePalette(struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vga_in8(0x3da, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) vga_out8(0x3c0, 0x00, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) par->paletteEnabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static inline void VGAdisablePalette(struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) vga_in8(0x3da, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) vga_out8(0x3c0, 0x20, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) par->paletteEnabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (par->paletteEnabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) index &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) index |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) vga_in8(0x3da, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) vga_out8(0x3c0, index, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) vga_out8 (0x3c0, value, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline void VGAwMISC(u8 value, struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) vga_out8(0x3c2, value, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #ifndef CONFIG_FB_SAVAGE_ACCEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define savagefb_set_clip(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline void VerticalRetraceWait(struct savagefb_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) vga_out8(0x3d4, 0x17, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (vga_in8(0x3d5, par) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) while ((vga_in8(0x3da, par) & 0x08) == 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) while ((vga_in8(0x3da, par) & 0x08) == 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) extern int savagefb_probe_i2c_connector(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 **out_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) extern void savagefb_create_i2c_busses(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) extern void savagefb_delete_i2c_busses(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) extern int savagefb_sync(struct fb_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) extern void savagefb_copyarea(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) const struct fb_copyarea *region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) extern void savagefb_fillrect(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const struct fb_fillrect *rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) extern void savagefb_imageblit(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const struct fb_image *image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif /* __SAVAGEFB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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