^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/sa1100fb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * -- StrongARM 1100 LCD Controller Frame Buffer Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 Eric A. Thomas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on acornfb.c Copyright (C) Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct gpio_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LCCR0 0x0000 /* LCD Control Reg. 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LCSR 0x0004 /* LCD Status Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DBAR1 0x0010 /* LCD DMA Base Address Reg. channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DCAR1 0x0014 /* LCD DMA Current Address Reg. channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DBAR2 0x0018 /* LCD DMA Base Address Reg. channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DCAR2 0x001C /* LCD DMA Current Address Reg. channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LCCR1 0x0020 /* LCD Control Reg. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LCCR2 0x0024 /* LCD Control Reg. 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LCCR3 0x0028 /* LCD Control Reg. 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Shadows for LCD controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct sa1100fb_lcd_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned long lccr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long lccr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long lccr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long lccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct sa1100fb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct fb_info fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const struct sa1100fb_rgb *rgb[NR_RGB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct gpio_desc *shannon_lcden;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * These are the addresses we mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * the framebuffer memory region to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dma_addr_t map_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u_char * map_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u_int map_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u_char * screen_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dma_addr_t screen_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 * palette_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dma_addr_t palette_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u_int palette_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma_addr_t dbar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dma_addr_t dbar2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u_int reg_lccr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u_int reg_lccr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u_int reg_lccr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u_int reg_lccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) volatile u_char state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) volatile u_char task_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mutex ctrlr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) wait_queue_head_t ctrlr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct work_struct task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct notifier_block freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct sa1100fb_mach_info *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TO_INF(ptr,member) container_of(ptr,struct sa1100fb_info,member)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SA1100_PALETTE_MODE_VAL(bpp) (((bpp) & 0x018) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * These are the actions for set_ctrlr_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define C_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define C_ENABLE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define C_DISABLE_CLKCHANGE (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define C_ENABLE_CLKCHANGE (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define C_REENABLE (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define C_DISABLE_PM (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define C_ENABLE_PM (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define C_STARTUP (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SA1100_NAME "SA1100"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Minimum X and Y resolutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MIN_XRES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MIN_YRES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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