^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/sa1100fb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1999 Eric A. Thomas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on acornfb.c Copyright (C) Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * StrongARM 1100 LCD Controller Frame Buffer Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Please direct your questions and comments on this driver to the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * email address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * linux-arm-kernel@lists.arm.linux.org.uk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Clean patches should be sent to the ARM Linux Patch System. Please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * following web page for more information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * https://www.arm.linux.org.uk/developer/patches/info.shtml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Thank you.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Known problems:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - With the Neponset plugged into an Assabet, LCD powerdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * doesn't work (LCD stays powered up). Therefore we shouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * blank the screen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - We don't limit the CPU clock rate nor the mode selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * according to the available SDRAM bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Other notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - Linear grayscale palettes and the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Such code does not belong in the kernel. The kernel frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * drivers do not expect a linear colourmap, but a colourmap based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * the VT100 standard mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * If your _userspace_ requires a linear colourmap, then the setup of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * such a colourmap belongs _in userspace_, not in the kernel. Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * to set the colourmap correctly from user space has been sent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * David Neuer. It's around 8 lines of C code, plus another 4 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * detect if we are using grayscale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * - The following must never be specified in a panel definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - The following should be specified:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * either LCCR0_Color or LCCR0_Mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * either LCCR0_Sngl or LCCR0_Dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * either LCCR0_Act or LCCR0_Pas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * either LCCR3_OutEnH or LCCD3_OutEnL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Code Status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 1999/04/01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * resolutions are working, but only the 8bpp mode is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Changes need to be made to the palette encode and decode routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * to support 4 and 16 bpp modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Driver is not designed to be a module. The FrameBuffer is statically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * allocated since dynamic allocation of a 300k buffer cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * guaranteed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 1999/06/17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - FrameBuffer memory is now allocated at run-time when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * driver is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 2000/04/10: Nicolas Pitre <nico@fluxnic.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * - Big cleanup for dynamic selection of machine type at run time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * - Support for Bitsy aka Compaq iPAQ H3600 added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Jeff Sutherland <jsutherland@accelent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * - Resolved an issue caused by a change made to the Assabet's PLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * earlier this year which broke the framebuffer driver for newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Phase 4 Assabets. Some other parameters were changed to optimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * for the Sharp display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * - XP860 support added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 2000/08/19: Mark Huang <mhuang@livetoy.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * - Allows standard options to be passed on the kernel command line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * for most common passive displays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 2000/08/29:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * - s/save_flags_cli/local_irq_save/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * - Updated LART stuff. Fixed some minor bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * - Pangolin support added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * - Huw Webpanel support added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 2000/11/23: Eric Peng <ericpeng@coventive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * - Freebird add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Cliff Brake <cbrake@accelent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * - Added PM callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * 2001/05/26: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * - Fix 16bpp so that (a) we use the right colours rather than some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * totally random colour depending on what was in page 0, and (b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * we don't de-reference a NULL pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * - remove duplicated implementation of consistent_alloc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * - convert dma address types to dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * - remove unused 'montype' stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * - remove redundant zero inits of init_var after the initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * memset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * - remove allow_modeset (acornfb idea does not belong here)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * 2001/05/28: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * - massive cleanup - move machine dependent data into structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * - I've left various #warnings in - if you see one, and know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * the hardware concerned, please get in contact with me.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * 2001/05/31: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * - Fix LCCR1 HSW value, fix all machine type specifications to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * keep values in line. (Please check your machine type specs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 2001/06/10: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * - Fiddle with the LCD controller from task context only; mainly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * so that we can run with interrupts on, and sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * - Convert #warnings into #errors. No pain, no gain. ;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 2001/06/14: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * - Make the palette BPS value for 12bpp come out correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * - Take notice of "greyscale" on any colour depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * - Make truecolor visuals use the RGB channel encoding information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 2001/07/02: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * - Fix colourmap problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 2001/07/13: <abraham@2d3d.co.za>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * - Added support for the ICP LCD-Kit01 on LART. This LCD is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * manufactured by Prime View, model no V16C6448AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * 2001/07/23: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * - Hand merge version from handhelds.org CVS tree. See patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * notes for 595/1 for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * - Drop 12bpp (it's 16bpp with different colour register mappings).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * - This hardware can not do direct colour. Therefore we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * support it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 2001/07/27: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * - Halve YRES on dual scan LCDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * 2001/08/22: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * - Add b/w iPAQ pixclock value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * 2001/10/12: <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * - Add patch 681/1 and clean up stork definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #include <video/sa1100fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #include <mach/shannon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Complain if VAR is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DEBUG_VAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #include "sa1100fb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct sa1100fb_rgb rgb_4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .red = { .offset = 0, .length = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .green = { .offset = 0, .length = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .blue = { .offset = 0, .length = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .transp = { .offset = 0, .length = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct sa1100fb_rgb rgb_8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .red = { .offset = 0, .length = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .green = { .offset = 0, .length = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .blue = { .offset = 0, .length = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .transp = { .offset = 0, .length = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct sa1100fb_rgb def_rgb_16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .red = { .offset = 11, .length = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .green = { .offset = 5, .length = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .blue = { .offset = 0, .length = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .transp = { .offset = 0, .length = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * We need to handle two requests being made at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * There are two important cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * We must perform the unblanking, which will do our REENABLE for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 2. When we are blanking, but immediately unblank before we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * blanked. We do the "REENABLE" thing here as well, just to be sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (fbi->task_state == C_ENABLE && state == C_REENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) state = (u_int) -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (fbi->task_state == C_DISABLE && state == C_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) state = C_REENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (state != (u_int)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) fbi->task_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) schedule_work(&fbi->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) chan &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) chan >>= 16 - bf->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return chan << bf->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Convert bits-per-pixel to a hardware palette PBS value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline u_int palette_pbs(struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case 4: ret = 0 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case 8: ret = 1 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 16: ret = 2 << 12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u_int trans, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct sa1100fb_info *fbi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) container_of(info, struct sa1100fb_info, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u_int val, ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (regno < fbi->palette_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val = ((red >> 4) & 0xf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val |= ((green >> 8) & 0x0f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) val |= ((blue >> 12) & 0x00f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (regno == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val |= palette_pbs(&fbi->fb.var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) fbi->palette_cpu[regno] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u_int trans, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct sa1100fb_info *fbi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) container_of(info, struct sa1100fb_info, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * If inverse mode was selected, invert all the colours
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * rather than the register number. The register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * is what you poke into the framebuffer to produce the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * colour you requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (fbi->inf->cmap_inverse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) red = 0xffff - red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) green = 0xffff - green;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) blue = 0xffff - blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * If greyscale is true, then we convert the RGB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * to greyscale no mater what visual we are using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (fbi->fb.var.grayscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) red = green = blue = (19595 * red + 38470 * green +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 7471 * blue) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) switch (fbi->fb.fix.visual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case FB_VISUAL_TRUECOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * 12 or 16-bit True Colour. We encode the RGB value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * according to the RGB bitfield information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (regno < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = chan_to_field(red, &fbi->fb.var.red);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val |= chan_to_field(green, &fbi->fb.var.green);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val |= chan_to_field(blue, &fbi->fb.var.blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fbi->pseudo_palette[regno] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case FB_VISUAL_STATIC_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case FB_VISUAL_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * sa1100fb_display_dma_period()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Calculate the minimum period (in picoseconds) between two DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * requests for the LCD controller. If we hit this, it means we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * doing nothing but LCD DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Period = pixclock * bits_per_byte * bytes_per_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * / memory_bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return var->pixclock * 8 * 16 / var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * sa1100fb_check_var():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Round up in the following order: bits_per_pixel, xres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * bitfields, horizontal timing, vertical timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct sa1100fb_info *fbi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) container_of(info, struct sa1100fb_info, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int rgbidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (var->xres < MIN_XRES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) var->xres = MIN_XRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (var->yres < MIN_YRES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) var->yres = MIN_YRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (var->xres > fbi->inf->xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) var->xres = fbi->inf->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (var->yres > fbi->inf->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) var->yres = fbi->inf->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) var->xres_virtual = max(var->xres_virtual, var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) var->yres_virtual = max(var->yres_virtual, var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_dbg(fbi->dev, "var->bits_per_pixel=%d\n", var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rgbidx = RGB_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rgbidx = RGB_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) rgbidx = RGB_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Copy the RGB parameters for this display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * from the machine specific parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) var->red = fbi->rgb[rgbidx]->red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) var->green = fbi->rgb[rgbidx]->green;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) var->blue = fbi->rgb[rgbidx]->blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) var->transp = fbi->rgb[rgbidx]->transp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_dbg(fbi->dev, "RGBT length = %d:%d:%d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) var->red.length, var->green.length, var->blue.length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) var->transp.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_dbg(fbi->dev, "RGBT offset = %d:%d:%d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) var->red.offset, var->green.offset, var->blue.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) var->transp.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_dbg(fbi->dev, "dma period = %d ps, clock = %ld kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sa1100fb_display_dma_period(var),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_get_rate(fbi->clk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void sa1100fb_set_visual(struct sa1100fb_info *fbi, u32 visual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (fbi->inf->set_visual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fbi->inf->set_visual(visual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * sa1100fb_set_par():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Set the user defined part of the display for the specified console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int sa1100fb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct sa1100fb_info *fbi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) container_of(info, struct sa1100fb_info, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long palette_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_dbg(fbi->dev, "set_par\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (var->bits_per_pixel == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) else if (!fbi->inf->cmap_static)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Some people have weird ideas about wanting static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * pseudocolor maps. I suspect their user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * applications are broken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fbi->fb.fix.line_length = var->xres_virtual *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) var->bits_per_pixel / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) palette_mem_size = fbi->palette_size * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_dbg(fbi->dev, "palette_mem_size = 0x%08lx\n", palette_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Set (any) board control register to handle new color depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sa1100fb_set_visual(fbi, fbi->fb.fix.visual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sa1100fb_activate_var(var, fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Make sure the user isn't doing something stupid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->inf->cmap_static))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return gen_set_cmap(cmap, kspc, con, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Formal definition of the VESA spec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * This refers to the state of the display when it is in full operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Stand-By
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * This defines an optional operating state of minimal power reduction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * the shortest recovery time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * This refers to a level of power management in which substantial power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * reduction is achieved by the display. The display can have a longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * recovery time from this state than from the Stand-by state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * This indicates that the display is consuming the lowest level of power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * and is non-operational. Recovery from this state may optionally require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * the user to manually power on the monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Now, the fbdev driver adds an additional state, (blank), where they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * turn off the video (maybe by colormap tricks), but don't mess with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * video itself: think of it semantically between on and Stand-By.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * So here's what we should do in our fbdev blank routine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * VESA_NO_BLANKING (mode 0) Video on, front/back light on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * VESA_POWERDOWN (mode 3) Video off, front/back light off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * This will match the matrox implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * sa1100fb_blank():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Blank the display by setting all palette values to zero. Note, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * 12 and 16 bpp modes don't really use the palette, so this will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * blank the display in all modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int sa1100fb_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct sa1100fb_info *fbi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) container_of(info, struct sa1100fb_info, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_dbg(fbi->dev, "sa1100fb_blank: blank=%d\n", blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) switch (blank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case FB_BLANK_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < fbi->palette_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sa1100fb_schedule_work(fbi, C_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case FB_BLANK_UNBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) fb_set_cmap(&fbi->fb.cmap, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sa1100fb_schedule_work(fbi, C_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int sa1100fb_mmap(struct fb_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct sa1100fb_info *fbi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) container_of(info, struct sa1100fb_info, fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (off < info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) vma->vm_pgoff += 1; /* skip over the palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return dma_mmap_wc(fbi->dev, vma, fbi->map_cpu, fbi->map_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fbi->map_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return vm_iomap_memory(vma, info->fix.mmio_start, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const struct fb_ops sa1100fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .fb_check_var = sa1100fb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .fb_set_par = sa1100fb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) // .fb_set_cmap = sa1100fb_set_cmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .fb_setcolreg = sa1100fb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .fb_blank = sa1100fb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .fb_mmap = sa1100fb_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Calculate the PCD value from the clock rate (in picoseconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * We take account of the PPCR clock setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static inline unsigned int get_pcd(struct sa1100fb_info *fbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int pixclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned int pcd = clk_get_rate(fbi->clk) / 100 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pcd *= pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pcd /= 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return pcd + 1; /* make up for integer math truncations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * sa1100fb_activate_var():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * Configures LCD Controller based on entries in var parameter. Settings are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * only written to the controller if changes were made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct sa1100fb_lcd_reg new_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u_int half_screen_size, yres, pcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u_long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(fbi->dev, "Configuring SA1100 LCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_dbg(fbi->dev, "var: xres=%d hslen=%d lm=%d rm=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) var->xres, var->hsync_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) var->left_margin, var->right_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev_dbg(fbi->dev, "var: yres=%d vslen=%d um=%d bm=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) var->yres, var->vsync_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) var->upper_margin, var->lower_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #if DEBUG_VAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (var->xres < 16 || var->xres > 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_err(fbi->dev, "%s: invalid xres %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fbi->fb.fix.id, var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (var->hsync_len < 1 || var->hsync_len > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(fbi->dev, "%s: invalid hsync_len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fbi->fb.fix.id, var->hsync_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (var->left_margin < 1 || var->left_margin > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_err(fbi->dev, "%s: invalid left_margin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fbi->fb.fix.id, var->left_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (var->right_margin < 1 || var->right_margin > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(fbi->dev, "%s: invalid right_margin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fbi->fb.fix.id, var->right_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (var->yres < 1 || var->yres > 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(fbi->dev, "%s: invalid yres %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) fbi->fb.fix.id, var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (var->vsync_len < 1 || var->vsync_len > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(fbi->dev, "%s: invalid vsync_len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fbi->fb.fix.id, var->vsync_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (var->upper_margin < 0 || var->upper_margin > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_err(fbi->dev, "%s: invalid upper_margin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fbi->fb.fix.id, var->upper_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (var->lower_margin < 0 || var->lower_margin > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_err(fbi->dev, "%s: invalid lower_margin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fbi->fb.fix.id, var->lower_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) new_regs.lccr0 = fbi->inf->lccr0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) new_regs.lccr1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) LCCR1_DisWdth(var->xres) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) LCCR1_HorSnchWdth(var->hsync_len) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) LCCR1_BegLnDel(var->left_margin) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) LCCR1_EndLnDel(var->right_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * If we have a dual scan LCD, then we need to halve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * the YRES parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) yres = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (fbi->inf->lccr0 & LCCR0_Dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) yres /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) new_regs.lccr2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) LCCR2_DisHght(yres) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) LCCR2_VrtSnchWdth(var->vsync_len) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) LCCR2_BegFrmDel(var->upper_margin) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) LCCR2_EndFrmDel(var->lower_margin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pcd = get_pcd(fbi, var->pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->inf->lccr3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_dbg(fbi->dev, "nlccr0 = 0x%08lx\n", new_regs.lccr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_dbg(fbi->dev, "nlccr1 = 0x%08lx\n", new_regs.lccr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_dbg(fbi->dev, "nlccr2 = 0x%08lx\n", new_regs.lccr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_dbg(fbi->dev, "nlccr3 = 0x%08lx\n", new_regs.lccr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) half_screen_size = var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) half_screen_size = half_screen_size * var->xres * var->yres / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Update shadow copy atomically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) fbi->dbar1 = fbi->palette_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) fbi->dbar2 = fbi->screen_dma + half_screen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) fbi->reg_lccr0 = new_regs.lccr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) fbi->reg_lccr1 = new_regs.lccr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fbi->reg_lccr2 = new_regs.lccr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) fbi->reg_lccr3 = new_regs.lccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Only update the registers if the controller is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * and something has changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (readl_relaxed(fbi->base + LCCR0) != fbi->reg_lccr0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) readl_relaxed(fbi->base + LCCR1) != fbi->reg_lccr1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) readl_relaxed(fbi->base + LCCR2) != fbi->reg_lccr2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) readl_relaxed(fbi->base + LCCR3) != fbi->reg_lccr3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) readl_relaxed(fbi->base + DBAR1) != fbi->dbar1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) readl_relaxed(fbi->base + DBAR2) != fbi->dbar2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) sa1100fb_schedule_work(fbi, C_REENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * NOTE! The following functions are purely helpers for set_ctrlr_state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Do not call them directly; set_ctrlr_state does the correct serialisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * to ensure that things happen in the right way 100% of time time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * -- rmk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_dbg(fbi->dev, "backlight o%s\n", on ? "n" : "ff");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (fbi->inf->backlight_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fbi->inf->backlight_power(on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_dbg(fbi->dev, "LCD power o%s\n", on ? "n" : "ff");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (fbi->inf->lcd_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) fbi->inf->lcd_power(on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u_int mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Enable GPIO<9:2> for LCD use if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * 1. Active display, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * 2. Color Dual Passive display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * see table 11.8 on page 11-27 in the SA1100 manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * -- Erik.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * SA1110 spec update nr. 25 says we can and should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * clear LDD15 to 12 for 4 or 8bpp modes with active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * panels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (fbi->fb.var.bits_per_pixel > 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * SA-1100 requires the GPIO direction register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * appropriately for the alternate function. Hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * we set it here via bitmask rather than excessive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * fiddling via the GPIO subsystem - and even then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * we'll still have to deal with GAFR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) GPDR |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GAFR |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_dbg(fbi->dev, "Enabling LCD controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * Make sure the mode bits are present in the first palette entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) fbi->palette_cpu[0] &= 0xcfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* enable LCD controller clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) clk_prepare_enable(fbi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Sequence from 11.7.10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) writel_relaxed(fbi->reg_lccr3, fbi->base + LCCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) writel_relaxed(fbi->reg_lccr2, fbi->base + LCCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) writel_relaxed(fbi->reg_lccr1, fbi->base + LCCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) writel_relaxed(fbi->dbar1, fbi->base + DBAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writel_relaxed(fbi->dbar2, fbi->base + DBAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (fbi->shannon_lcden)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) gpiod_set_value(fbi->shannon_lcden, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_dbg(fbi->dev, "DBAR1: 0x%08x\n", readl_relaxed(fbi->base + DBAR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_dbg(fbi->dev, "DBAR2: 0x%08x\n", readl_relaxed(fbi->base + DBAR2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_dbg(fbi->dev, "LCCR0: 0x%08x\n", readl_relaxed(fbi->base + LCCR0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_dbg(fbi->dev, "LCCR1: 0x%08x\n", readl_relaxed(fbi->base + LCCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_dbg(fbi->dev, "LCCR2: 0x%08x\n", readl_relaxed(fbi->base + LCCR2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_dbg(fbi->dev, "LCCR3: 0x%08x\n", readl_relaxed(fbi->base + LCCR3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 lccr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_dbg(fbi->dev, "Disabling LCD controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (fbi->shannon_lcden)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) gpiod_set_value(fbi->shannon_lcden, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) add_wait_queue(&fbi->ctrlr_wait, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Clear LCD Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) writel_relaxed(~0, fbi->base + LCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) lccr0 = readl_relaxed(fbi->base + LCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) lccr0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) writel_relaxed(lccr0, fbi->base + LCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) lccr0 &= ~LCCR0_LEN; /* Disable LCD Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) writel_relaxed(lccr0, fbi->base + LCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) schedule_timeout(20 * HZ / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) remove_wait_queue(&fbi->ctrlr_wait, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* disable LCD controller clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) clk_disable_unprepare(fbi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct sa1100fb_info *fbi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned int lcsr = readl_relaxed(fbi->base + LCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (lcsr & LCSR_LDD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 lccr0 = readl_relaxed(fbi->base + LCCR0) | LCCR0_LDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) writel_relaxed(lccr0, fbi->base + LCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) wake_up(&fbi->ctrlr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) writel_relaxed(lcsr, fbi->base + LCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * This function must be called from task context only, since it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * sleep when disabling the LCD controller, or if we get two contending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * processes trying to alter state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u_int old_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mutex_lock(&fbi->ctrlr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) old_state = fbi->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Hack around fbcon initialisation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (old_state == C_STARTUP && state == C_REENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) state = C_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case C_DISABLE_CLKCHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * Disable controller for clock change. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * controller is already disabled, then do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) fbi->state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) sa1100fb_disable_controller(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case C_DISABLE_PM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case C_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Disable controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (old_state != C_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) fbi->state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) __sa1100fb_backlight_power(fbi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (old_state != C_DISABLE_CLKCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) sa1100fb_disable_controller(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __sa1100fb_lcd_power(fbi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case C_ENABLE_CLKCHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * Enable the controller after clock change. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * do this if we were disabled for the clock change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (old_state == C_DISABLE_CLKCHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) fbi->state = C_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) sa1100fb_enable_controller(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case C_REENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * Re-enable the controller only if it was already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * enabled. This is so we reprogram the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (old_state == C_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) sa1100fb_disable_controller(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) sa1100fb_setup_gpio(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) sa1100fb_enable_controller(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case C_ENABLE_PM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Re-enable the controller after PM. This is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * perfect - think about the case where we were doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * a clock change, and we suspended half-way through.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (old_state != C_DISABLE_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) case C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * Power up the LCD screen, enable controller, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * turn on the backlight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (old_state != C_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fbi->state = C_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sa1100fb_setup_gpio(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) __sa1100fb_lcd_power(fbi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) sa1100fb_enable_controller(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __sa1100fb_backlight_power(fbi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mutex_unlock(&fbi->ctrlr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * Our LCD controller task (which is called when we blank or unblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * via keventd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static void sa1100fb_task(struct work_struct *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u_int state = xchg(&fbi->task_state, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) set_ctrlr_state(fbi, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * CPU clock speed change handler. We need to adjust the LCD timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * parameters when the CPU clock is adjusted by the power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u_int pcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case CPUFREQ_PRECHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) case CPUFREQ_POSTCHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pcd = get_pcd(fbi, fbi->fb.var.pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * Power management hooks. Note that we won't be called from IRQ context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * unlike the blank functions above, so we may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct sa1100fb_info *fbi = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) set_ctrlr_state(fbi, C_DISABLE_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int sa1100fb_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct sa1100fb_info *fbi = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) set_ctrlr_state(fbi, C_ENABLE_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define sa1100fb_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define sa1100fb_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * sa1100fb_map_video_memory():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Allocates the DRAM memory for the frame buffer. This buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * remapped into a non-cached, non-buffered, memory region to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * allow palette and pixel writes to occur without flushing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * cache. Once this area is remapped, all virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * access to the video memory should occur at the new region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * We reserve one page for the palette, plus the size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * of the framebuffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) fbi->map_cpu = dma_alloc_wc(fbi->dev, fbi->map_size, &fbi->map_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (fbi->map_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * FIXME: this is actually the wrong thing to place in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * smem_start. But fbdev suffers from the problem that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * it needs an API which doesn't exist (in this case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * dma_writecombine_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) fbi->fb.fix.smem_start = fbi->screen_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return fbi->map_cpu ? 0 : -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Fake monspecs to fill in fbinfo structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const struct fb_monspecs monspecs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .hfmin = 30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .hfmax = 70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .vfmin = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .vfmax = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static struct sa1100fb_info *sa1100fb_init_fbinfo(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct sa1100fb_mach_info *inf = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct sa1100fb_info *fbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) fbi = devm_kzalloc(dev, sizeof(struct sa1100fb_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) fbi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) strcpy(fbi->fb.fix.id, SA1100_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) fbi->fb.fix.type_aux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) fbi->fb.fix.xpanstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) fbi->fb.fix.ypanstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) fbi->fb.fix.ywrapstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) fbi->fb.fix.accel = FB_ACCEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) fbi->fb.var.nonstd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) fbi->fb.var.activate = FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) fbi->fb.var.height = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) fbi->fb.var.width = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) fbi->fb.var.accel_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) fbi->fb.fbops = &sa1100fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fbi->fb.flags = FBINFO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) fbi->fb.monspecs = monspecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) fbi->fb.pseudo_palette = fbi->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) fbi->rgb[RGB_4] = &rgb_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) fbi->rgb[RGB_8] = &rgb_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) fbi->rgb[RGB_16] = &def_rgb_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * People just don't seem to get this. We don't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * anything but correct entries now, so panic if someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * does something stupid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) inf->pixclock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) panic("sa1100fb error: invalid LCCR3 fields set or zero "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) "pixclock.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) fbi->fb.var.xres = inf->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) fbi->fb.var.xres_virtual = inf->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fbi->fb.var.yres = inf->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) fbi->fb.var.yres_virtual = inf->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) fbi->fb.var.bits_per_pixel = inf->bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) fbi->fb.var.pixclock = inf->pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) fbi->fb.var.hsync_len = inf->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) fbi->fb.var.left_margin = inf->left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) fbi->fb.var.right_margin = inf->right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) fbi->fb.var.vsync_len = inf->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) fbi->fb.var.upper_margin = inf->upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) fbi->fb.var.lower_margin = inf->lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) fbi->fb.var.sync = inf->sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) fbi->fb.var.grayscale = inf->cmap_greyscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) fbi->state = C_STARTUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) fbi->task_state = (u_char)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) fbi->fb.fix.smem_len = inf->xres * inf->yres *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) inf->bpp / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) fbi->inf = inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* Copy the RGB bitfield overrides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) for (i = 0; i < NR_RGB; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (inf->rgb[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fbi->rgb[i] = inf->rgb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) init_waitqueue_head(&fbi->ctrlr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) INIT_WORK(&fbi->task, sa1100fb_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mutex_init(&fbi->ctrlr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return fbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int sa1100fb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct sa1100fb_info *fbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!dev_get_platdata(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_err(&pdev->dev, "no platform LCD data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) fbi = sa1100fb_init_fbinfo(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!fbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) fbi->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (IS_ERR(fbi->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return PTR_ERR(fbi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) fbi->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (IS_ERR(fbi->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return PTR_ERR(fbi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = devm_request_irq(&pdev->dev, irq, sa1100fb_handle_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) "LCD", fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_err(&pdev->dev, "request_irq failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) fbi->shannon_lcden = gpiod_get_optional(&pdev->dev, "shannon-lcden",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (IS_ERR(fbi->shannon_lcden))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return PTR_ERR(fbi->shannon_lcden);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Initialize video memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = sa1100fb_map_video_memory(fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * This makes sure that our colour bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * descriptors are correctly initialised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) platform_set_drvdata(pdev, fbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = register_framebuffer(&fbi->fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dma_free_wc(fbi->dev, fbi->map_size, fbi->map_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) fbi->map_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* This driver cannot be unloaded at the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static struct platform_driver sa1100fb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .probe = sa1100fb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .suspend = sa1100fb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .resume = sa1100fb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .name = "sa11x0-fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int __init sa1100fb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (fb_get_options("sa1100fb", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return platform_driver_register(&sa1100fb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int __init sa1100fb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) char *this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) while ((this_opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!strncmp(this_opt, "bpp:", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) current_par.max_bpp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) simple_strtoul(this_opt + 4, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!strncmp(this_opt, "lccr0:", 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) lcd_shadow.lccr0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) simple_strtoul(this_opt + 6, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!strncmp(this_opt, "lccr1:", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) lcd_shadow.lccr1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) simple_strtoul(this_opt + 6, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) current_par.max_xres =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) (lcd_shadow.lccr1 & 0x3ff) + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (!strncmp(this_opt, "lccr2:", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) lcd_shadow.lccr2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) simple_strtoul(this_opt + 6, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) current_par.max_yres =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) (lcd_shadow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) lccr0 & LCCR0_SDS) ? ((lcd_shadow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) lccr2 & 0x3ff) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (!strncmp(this_opt, "lccr3:", 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) lcd_shadow.lccr3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) simple_strtoul(this_opt + 6, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) module_init(sa1100fb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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