^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * which is based on the code of neofb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/svga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct s3fb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int chip, rev, mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct vgastate state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mutex open_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifdef CONFIG_FB_S3_DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool ddc_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct i2c_adapter ddc_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct i2c_algo_bit_data ddc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct svga_fb_format s3fb_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SVGA_FORMAT_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 35000, 240000, 14318};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 230000, 460000, 14318};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "S3 Virge/GX2", "S3 Virge/GX2+", "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "S3 Trio3D", "S3 Virge/MX"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CHIP_UNKNOWN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CHIP_732_TRIO32 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CHIP_764_TRIO64 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CHIP_765_TRIO64VP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CHIP_767_TRIO64UVP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CHIP_775_TRIO64V2_DX 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CHIP_785_TRIO64V2_GX 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CHIP_551_PLATO_PX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CHIP_M65_AURORA64VP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CHIP_325_VIRGE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CHIP_988_VIRGE_VX 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CHIP_375_VIRGE_DX 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CHIP_385_VIRGE_GX 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CHIP_357_VIRGE_GX2 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CHIP_359_VIRGE_GX2P 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CHIP_360_TRIO3D_1X 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CHIP_362_TRIO3D_2X 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CHIP_368_TRIO3D_2X 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CHIP_365_TRIO3D 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CHIP_260_VIRGE_MX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CHIP_XXX_TRIO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CHIP_XXX_TRIO64V2_DXGX 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CHIP_XXX_VIRGE_DXGX 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CHIP_36X_TRIO3D_1X_2X 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CHIP_UNDECIDED_FLAG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CHIP_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MMIO_OFFSET 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MMIO_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* CRT timing register sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct svga_timing_regs s3_timing_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static char *mode_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int mtrr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int fasttext = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) module_param(mode_option, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) module_param_named(mode, mode_option, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) module_param(mtrr, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) module_param(fasttext, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifdef CONFIG_FB_S3_DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DDC_REG 0xaa /* Trio 3D/1X/2X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DDC_MMIO_REG 0xff20 /* all other chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DDC_SCL_OUT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DDC_SDA_OUT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DDC_SCL_IN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DDC_SDA_IN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DDC_DRIVE_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static bool s3fb_ddc_needs_mmio(int chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return !(chip == CHIP_360_TRIO3D_1X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) chip == CHIP_362_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) chip == CHIP_368_TRIO3D_2X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static u8 s3fb_ddc_read(struct s3fb_info *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (s3fb_ddc_needs_mmio(par->chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return readb(par->mmio + DDC_MMIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return vga_rcrt(par->state.vgabase, DDC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (s3fb_ddc_needs_mmio(par->chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writeb(val, par->mmio + DDC_MMIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) vga_wcrt(par->state.vgabase, DDC_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void s3fb_ddc_setscl(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct s3fb_info *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg |= DDC_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg &= ~DDC_SCL_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) s3fb_ddc_write(par, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void s3fb_ddc_setsda(void *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct s3fb_info *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg |= DDC_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) reg &= ~DDC_SDA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) s3fb_ddc_write(par, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int s3fb_ddc_getscl(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct s3fb_info *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int s3fb_ddc_getsda(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct s3fb_info *par = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int s3fb_setup_ddc_bus(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) strlcpy(par->ddc_adapter.name, info->fix.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sizeof(par->ddc_adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) par->ddc_adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) par->ddc_adapter.class = I2C_CLASS_DDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) par->ddc_adapter.algo_data = &par->ddc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) par->ddc_adapter.dev.parent = info->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) par->ddc_algo.setsda = s3fb_ddc_setsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) par->ddc_algo.setscl = s3fb_ddc_setscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) par->ddc_algo.getsda = s3fb_ddc_getsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) par->ddc_algo.getscl = s3fb_ddc_getscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) par->ddc_algo.udelay = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) par->ddc_algo.timeout = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) par->ddc_algo.data = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) i2c_set_adapdata(&par->ddc_adapter, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * some Virge cards have external MUX to switch chip I2C bus between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * DDC and extension pins - switch it do DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (par->chip == CHIP_357_VIRGE_GX2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) par->chip == CHIP_359_VIRGE_GX2P ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) par->chip == CHIP_260_VIRGE_MX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* some Virge need this or the DDC is ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return i2c_bit_add_bus(&par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif /* CONFIG_FB_S3_DDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Set font in S3 fast text mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const u8 *font = map->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 __iomem *fb = (u8 __iomem *) info->screen_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int i, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if ((map->width != 8) || (map->height != 16) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (map->depth != 1) || (map->length != 256)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) map->width, map->height, map->depth, map->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) fb += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < map->height; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for (c = 0; c < map->length; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) fb_writeb(font[c * map->height + i], fb + c * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) fb += 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) svga_tilecursor(par->state.vgabase, info, cursor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct fb_tile_ops s3fb_tile_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .fb_settile = svga_settile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .fb_tilecopy = svga_tilecopy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .fb_tilefill = svga_tilefill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .fb_tileblit = svga_tileblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .fb_tilecursor = s3fb_tilecursor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .fb_get_tilemax = svga_get_tilemax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct fb_tile_ops s3fb_fast_tile_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .fb_settile = s3fb_settile_fast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .fb_tilecopy = svga_tilecopy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .fb_tilefill = svga_tilefill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .fb_tileblit = svga_tileblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .fb_tilecursor = s3fb_tilecursor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .fb_get_tilemax = svga_get_tilemax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* image data is MSB-first, fb structure is MSB-first too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static inline u32 expand_color(u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 fg = expand_color(image->fg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 bg = expand_color(image->bg_color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) const u8 *src1, *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 __iomem *dst1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 __iomem *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) src1 = image->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dst1 = info->screen_base + (image->dy * info->fix.line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) + ((image->dx / 8) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for (y = 0; y < image->height; y++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) src = src1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dst = (u32 __iomem *) dst1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (x = 0; x < image->width; x += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = *(src++) * 0x01010101;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val = (val & fg) | (~val & bg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fb_writel(val, dst++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) src1 += image->width / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dst1 += info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 fg = expand_color(rect->color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 __iomem *dst1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 __iomem *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dst1 = info->screen_base + (rect->dy * info->fix.line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) + ((rect->dx / 8) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (y = 0; y < rect->height; y++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dst = (u32 __iomem *) dst1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (x = 0; x < rect->width; x += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) fb_writel(fg, dst++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dst1 += info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline u32 expand_pixel(u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 fg = image->fg_color * 0x11111111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 bg = image->bg_color * 0x11111111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const u8 *src1, *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 __iomem *dst1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 __iomem *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) src1 = image->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dst1 = info->screen_base + (image->dy * info->fix.line_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) + ((image->dx / 8) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (y = 0; y < image->height; y++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) src = src1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dst = (u32 __iomem *) dst1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for (x = 0; x < image->width; x += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val = expand_pixel(*(src++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val = (val & fg) | (~val & bg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) fb_writel(val, dst++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) src1 += image->width / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dst1 += info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) s3fb_iplan_imageblit(info, image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) s3fb_cfb4_imageblit(info, image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cfb_imageblit(info, image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if ((info->var.bits_per_pixel == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) s3fb_iplan_fillrect(info, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cfb_fillrect(info, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u16 m, n, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 1000000000 / pixclock, &m, &n, &r, info->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fb_err(info, "cannot set requested pixclock, keeping old value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Set VGA misc register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) regval = vga_r(par->state.vgabase, VGA_MIS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Set S3 clock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (par->chip == CHIP_357_VIRGE_GX2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) par->chip == CHIP_359_VIRGE_GX2P ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) par->chip == CHIP_360_TRIO3D_1X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) par->chip == CHIP_362_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) par->chip == CHIP_368_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) par->chip == CHIP_260_VIRGE_MX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) vga_wseq(par->state.vgabase, 0x13, m - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Open framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int s3fb_open(struct fb_info *info, int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mutex_lock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (par->ref_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void __iomem *vgabase = par->state.vgabase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) memset(&(par->state), 0, sizeof(struct vgastate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) par->state.vgabase = vgabase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) par->state.num_crtc = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) par->state.num_seq = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) save_vga(&(par->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) par->ref_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Close framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int s3fb_release(struct fb_info *info, int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mutex_lock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (par->ref_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (par->ref_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) restore_vga(&(par->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) par->ref_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Validate passed in var */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int rv, mem, step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u16 m, n, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Find appropriate format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rv = svga_match_format (s3fb_formats, var, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* 32bpp mode is not supported on VIRGE VX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 24bpp is not supported on others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rv = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) fb_err(info, "unsupported mode requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Do not allow to have real resoulution larger than virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (var->xres > var->xres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (var->yres > var->yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Round up xres_virtual to have proper alignment of lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) step = s3fb_formats[rv].xresstep - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) var->xres_virtual = (var->xres_virtual+step) & ~step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Check whether have enough memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (mem > info->screen_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mem >> 10, (unsigned int) (info->screen_size >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) rv = svga_check_timings (&s3_timing_regs, var, info->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fb_err(info, "invalid timings requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) info->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) fb_err(info, "invalid pixclock value requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Set video mode from par */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int s3fb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 bpp = info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 htotal, hsstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (bpp != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) info->fix.ypanstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) info->flags &= ~FBINFO_MISC_TILEBLITTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) info->tileops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) info->pixmap.blit_y = ~(u32)0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) offset_value = (info->var.xres_virtual * bpp) / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) screen_size = info->var.yres_virtual * info->fix.line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) info->fix.ypanstep = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) info->fix.line_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) info->flags |= FBINFO_MISC_TILEBLITTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* supports 8x16 tiles only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) info->pixmap.blit_x = 1 << (8 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) info->pixmap.blit_y = 1 << (16 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) offset_value = info->var.xres_virtual / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) info->var.xoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) info->var.yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) info->var.activate = FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Unlock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vga_wcrt(par->state.vgabase, 0x38, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) vga_wcrt(par->state.vgabase, 0x39, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) vga_wseq(par->state.vgabase, 0x08, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Blank screen and turn off sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Set default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) svga_set_default_gfx_regs(par->state.vgabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) svga_set_default_atc_regs(par->state.vgabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) svga_set_default_seq_regs(par->state.vgabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) svga_set_default_crt_regs(par->state.vgabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* S3 specific initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Set the offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fb_dbg(info, "offset register : %d\n", offset_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (par->chip != CHIP_357_VIRGE_GX2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) par->chip != CHIP_359_VIRGE_GX2P &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) par->chip != CHIP_360_TRIO3D_1X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) par->chip != CHIP_362_TRIO3D_2X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) par->chip != CHIP_368_TRIO3D_2X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) par->chip != CHIP_260_VIRGE_MX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) vga_wcrt(par->state.vgabase, 0x3A, 0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) svga_wattr(par->state.vgabase, 0x33, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (info->var.vmode & FB_VMODE_DOUBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (info->var.vmode & FB_VMODE_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Disable hardware graphics cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Disable Streams engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* S3 virge DX hack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (par->chip == CHIP_375_VIRGE_DX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) vga_wcrt(par->state.vgabase, 0x86, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) vga_wcrt(par->state.vgabase, 0x90, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* S3 virge VX hack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (par->chip == CHIP_988_VIRGE_VX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) vga_wcrt(par->state.vgabase, 0x50, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) vga_wcrt(par->state.vgabase, 0x67, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) msleep(10); /* screen remains blank sometimes without this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) vga_wcrt(par->state.vgabase, 0x66, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (par->chip == CHIP_357_VIRGE_GX2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) par->chip == CHIP_359_VIRGE_GX2P ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) par->chip == CHIP_360_TRIO3D_1X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) par->chip == CHIP_362_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) par->chip == CHIP_368_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) par->chip == CHIP_365_TRIO3D ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) par->chip == CHIP_375_VIRGE_DX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) par->chip == CHIP_385_VIRGE_GX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) par->chip == CHIP_260_VIRGE_MX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dbytes = info->var.xres * ((bpp+7)/8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) vga_wcrt(par->state.vgabase, 0x66, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (par->chip == CHIP_357_VIRGE_GX2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) par->chip == CHIP_359_VIRGE_GX2P ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) par->chip == CHIP_360_TRIO3D_1X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) par->chip == CHIP_362_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) par->chip == CHIP_368_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) par->chip == CHIP_260_VIRGE_MX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) vga_wcrt(par->state.vgabase, 0x34, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else /* enable Data Transfer Position Control (DTPC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) vga_wcrt(par->state.vgabase, 0x34, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) multiplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) hmul = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Set mode-specific register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fb_dbg(info, "text mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) svga_set_textmode_vga_regs(par->state.vgabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Set additional registers like in 8-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Disable enhanced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (fasttext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fb_dbg(info, "high speed text mode set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fb_dbg(info, "4 bit pseudocolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Set additional registers like in 8-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* disable enhanced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) fb_dbg(info, "4 bit pseudocolor, planar\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Set additional registers like in 8-bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* disable enhanced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fb_dbg(info, "8 bit pseudocolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (info->var.pixclock > 20000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) par->chip == CHIP_357_VIRGE_GX2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) par->chip == CHIP_359_VIRGE_GX2P ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) par->chip == CHIP_360_TRIO3D_1X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) par->chip == CHIP_362_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) par->chip == CHIP_368_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) par->chip == CHIP_260_VIRGE_MX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) multiplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) fb_dbg(info, "5/5/5 truecolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (par->chip == CHIP_988_VIRGE_VX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (info->var.pixclock > 20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else if (par->chip == CHIP_365_TRIO3D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (info->var.pixclock > 8695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) hmul = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) multiplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (par->chip != CHIP_357_VIRGE_GX2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) par->chip != CHIP_359_VIRGE_GX2P &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) par->chip != CHIP_360_TRIO3D_1X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) par->chip != CHIP_362_TRIO3D_2X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) par->chip != CHIP_368_TRIO3D_2X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) par->chip != CHIP_260_VIRGE_MX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) hmul = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) fb_dbg(info, "5/6/5 truecolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (par->chip == CHIP_988_VIRGE_VX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (info->var.pixclock > 20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) } else if (par->chip == CHIP_365_TRIO3D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (info->var.pixclock > 8695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) hmul = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) multiplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (par->chip != CHIP_357_VIRGE_GX2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) par->chip != CHIP_359_VIRGE_GX2P &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) par->chip != CHIP_360_TRIO3D_1X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) par->chip != CHIP_362_TRIO3D_2X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) par->chip != CHIP_368_TRIO3D_2X &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) par->chip != CHIP_260_VIRGE_MX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) hmul = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* VIRGE VX case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) fb_dbg(info, "8/8/8 truecolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) fb_dbg(info, "8/8/8/8 truecolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) fb_err(info, "unsupported mode - bug\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (par->chip != CHIP_988_VIRGE_VX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) s3_set_pixclock(info, info->var.pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) hmul, info->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Set interlaced mode start/end register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) htotal = ((htotal * hmul) / 8) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Set Data Transfer Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* + 2 is needed for Virge/VX, does no harm on other cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) memset_io(info->screen_base, 0x00, screen_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Device and screen back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* Set a colour register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u_int transp, struct fb_info *fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) switch (fb->var.bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (regno >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if ((fb->var.bits_per_pixel == 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) (fb->var.nonstd == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) outb(0xF0, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) outb(regno*16, VGA_PEL_IW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) outb(0x0F, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) outb(regno, VGA_PEL_IW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) outb(red >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) outb(green >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) outb(blue >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (regno >= 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) outb(0xFF, VGA_PEL_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) outb(regno, VGA_PEL_IW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) outb(red >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) outb(green >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) outb(blue >> 10, VGA_PEL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (regno >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (fb->var.green.length == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) else if (fb->var.green.length == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) else return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (regno >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) (green & 0xFF00) | ((blue & 0xFF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Set the display blanking state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int s3fb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) switch (blank_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case FB_BLANK_UNBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) fb_dbg(info, "unblank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case FB_BLANK_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) fb_dbg(info, "blank\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) fb_dbg(info, "hsync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) fb_dbg(info, "vsync\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) fb_dbg(info, "sync down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Pan the display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Calculate the offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (info->var.bits_per_pixel == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) + (var->xoffset / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) offset = offset >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) offset = (var->yoffset * info->fix.line_length) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) (var->xoffset * info->var.bits_per_pixel / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) offset = offset >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Set the offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Frame buffer operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct fb_ops s3fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .fb_open = s3fb_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .fb_release = s3fb_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .fb_check_var = s3fb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .fb_set_par = s3fb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .fb_setcolreg = s3fb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .fb_blank = s3fb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .fb_pan_display = s3fb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .fb_fillrect = s3fb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .fb_imageblit = s3fb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .fb_get_caps = svga_get_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int s3_identification(struct s3fb_info *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int chip = par->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (chip == CHIP_XXX_TRIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (cr2e == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return CHIP_732_TRIO32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (cr2e == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (! (cr2f & 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return CHIP_764_TRIO64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return CHIP_765_TRIO64VP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (chip == CHIP_XXX_TRIO64V2_DXGX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (! (cr6f & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return CHIP_775_TRIO64V2_DX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return CHIP_785_TRIO64V2_GX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (chip == CHIP_XXX_VIRGE_DXGX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (! (cr6f & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return CHIP_375_VIRGE_DX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return CHIP_385_VIRGE_GX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (chip == CHIP_36X_TRIO3D_1X_2X) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) switch (vga_rcrt(par->state.vgabase, 0x2f)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return CHIP_360_TRIO3D_1X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return CHIP_362_TRIO3D_2X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return CHIP_368_TRIO3D_2X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return CHIP_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* PCI probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct pci_bus_region bus_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct resource vga_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct s3fb_info *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) u8 regval, cr38, cr39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Ignore secondary VGA device because there is no VGA arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (! svga_primary_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_info(&(dev->dev), "ignoring secondary device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Allocate and fill driver data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mutex_init(&par->open_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) info->fbops = &s3fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Prepare PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) rc = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_err(info->device, "cannot enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) goto err_enable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) rc = pci_request_regions(dev, "s3fb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_err(info->device, "cannot reserve framebuffer region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) goto err_request_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) info->fix.smem_start = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) info->fix.smem_len = pci_resource_len(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Map physical IO memory address into kernel space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) info->screen_base = pci_iomap_wc(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (! info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_err(info->device, "iomap for framebuffer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) goto err_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) bus_reg.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) bus_reg.end = 64 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) vga_res.flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Unlock regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) cr38 = vga_rcrt(par->state.vgabase, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) cr39 = vga_rcrt(par->state.vgabase, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) vga_wseq(par->state.vgabase, 0x08, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) vga_wcrt(par->state.vgabase, 0x38, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) vga_wcrt(par->state.vgabase, 0x39, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Identify chip type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) par->chip = id->driver_data & CHIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) par->rev = vga_rcrt(par->state.vgabase, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (par->chip & CHIP_UNDECIDED_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) par->chip = s3_identification(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Find how many physical memory there is on card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* 0x36 register is accessible even if other registers are locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) regval = vga_rcrt(par->state.vgabase, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (par->chip == CHIP_360_TRIO3D_1X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) par->chip == CHIP_362_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) par->chip == CHIP_368_TRIO3D_2X ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) par->chip == CHIP_365_TRIO3D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) switch ((regval & 0xE0) >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) case 0: /* 8MB -- only 4MB usable for display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) case 1: /* 4MB with 32-bit bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case 2: /* 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) info->screen_size = 4 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case 4: /* 2MB on 365 Trio3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) case 6: /* 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) info->screen_size = 2 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) } else if (par->chip == CHIP_357_VIRGE_GX2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) par->chip == CHIP_359_VIRGE_GX2P ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) par->chip == CHIP_260_VIRGE_MX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) switch ((regval & 0xC0) >> 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) case 1: /* 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) info->screen_size = 4 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case 3: /* 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) info->screen_size = 2 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) } else if (par->chip == CHIP_988_VIRGE_VX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) switch ((regval & 0x60) >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) case 0: /* 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) info->screen_size = 2 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) case 1: /* 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) info->screen_size = 4 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) case 2: /* 6MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) info->screen_size = 6 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case 3: /* 8MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) info->screen_size = 8 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* off-screen memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) regval = vga_rcrt(par->state.vgabase, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) switch ((regval & 0x60) >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) case 1: /* 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) info->screen_size -= 4 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case 2: /* 2MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) info->screen_size -= 2 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) info->screen_size = s3_memsizes[regval >> 5] << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) info->fix.smem_len = info->screen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Find MCLK frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) regval = vga_rseq(par->state.vgabase, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) par->mclk_freq = par->mclk_freq >> (regval >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Restore locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) vga_wcrt(par->state.vgabase, 0x38, cr38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) vga_wcrt(par->state.vgabase, 0x39, cr39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) strcpy(info->fix.id, s3_names [par->chip]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) info->fix.mmio_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) info->fix.mmio_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) info->fix.type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) info->fix.ypanstep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) info->fix.accel = FB_ACCEL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) info->pseudo_palette = (void*) (par->pseudo_palette);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) info->var.bits_per_pixel = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #ifdef CONFIG_FB_S3_DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Enable MMIO if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (s3fb_ddc_needs_mmio(par->chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (par->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) info->fix.smem_start + MMIO_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (s3fb_setup_ddc_bus(info) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u8 *edid = fb_ddc_read(&par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) par->ddc_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) fb_edid_to_monspecs(edid, &info->monspecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) kfree(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!info->monspecs.modedb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dev_err(info->device, "error getting mode database\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) const struct fb_videomode *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) fb_videomode_to_modelist(info->monspecs.modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) info->monspecs.modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) m = fb_find_best_display(&info->monspecs, &info->modelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) fb_videomode_to_var(&info->var, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* fill all other info->var's fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (s3fb_check_var(&info->var, info) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (!mode_option && !found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) mode_option = "640x480-8@60";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Prepare startup mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (mode_option) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) rc = fb_find_mode(&info->var, info, mode_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) info->monspecs.modedb, info->monspecs.modedb_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) NULL, info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (!rc || rc == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_err(info->device, "mode %s not found\n", mode_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) fb_destroy_modedb(info->monspecs.modedb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) info->monspecs.modedb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) goto err_find_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) fb_destroy_modedb(info->monspecs.modedb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) info->monspecs.modedb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* maximize virtual vertical size for fast scrolling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) info->var.yres_virtual = info->fix.smem_len * 8 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) (info->var.bits_per_pixel * info->var.xres_virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (info->var.yres_virtual < info->var.yres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_err(info->device, "virtual vertical size smaller than real\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) goto err_find_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) rc = fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_err(info->device, "cannot allocate colormap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) goto err_alloc_cmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) rc = register_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev_err(info->device, "cannot register framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) goto err_reg_fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) info->fix.id, pci_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (par->chip == CHIP_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) vga_rcrt(par->state.vgabase, 0x2d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) vga_rcrt(par->state.vgabase, 0x2e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) vga_rcrt(par->state.vgabase, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) vga_rcrt(par->state.vgabase, 0x30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Record a reference to the driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pci_set_drvdata(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (mtrr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* Error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) err_reg_fb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) err_alloc_cmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) err_find_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #ifdef CONFIG_FB_S3_DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (par->ddc_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) i2c_del_adapter(&par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (par->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) iounmap(par->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) pci_iounmap(dev, info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) err_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) err_request_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* pci_disable_device(dev); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) err_enable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* PCI remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static void s3_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct fb_info *info = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct s3fb_info __maybe_unused *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) arch_phys_wc_del(par->wc_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #ifdef CONFIG_FB_S3_DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (par->ddc_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) i2c_del_adapter(&par->ddc_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (par->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) iounmap(par->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pci_iounmap(dev, info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* pci_disable_device(dev); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* PCI suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static int __maybe_unused s3_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dev_info(info->device, "suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) console_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mutex_lock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (par->ref_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) console_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) fb_set_suspend(info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) console_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* PCI resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static int __maybe_unused s3_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct fb_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct s3fb_info *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) dev_info(info->device, "resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) console_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) mutex_lock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (par->ref_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) console_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) s3fb_set_par(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) fb_set_suspend(info, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mutex_unlock(&(par->open_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) console_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static const struct dev_pm_ops s3_pci_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .suspend = s3_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .resume = s3_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .freeze = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .thaw = s3_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .poweroff = s3_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .restore = s3_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* List of boards that we are trying to support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const struct pci_device_id s3_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {0, 0, 0, 0, 0, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) MODULE_DEVICE_TABLE(pci, s3_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static struct pci_driver s3fb_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .name = "s3fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .id_table = s3_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .probe = s3_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .remove = s3_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .driver.pm = &s3_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Parse user specified options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static int __init s3fb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) char *opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) while ((opt = strsep(&options, ",")) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (!*opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) else if (!strncmp(opt, "mtrr:", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) mtrr = simple_strtoul(opt + 5, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) else if (!strncmp(opt, "fasttext:", 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) fasttext = simple_strtoul(opt + 9, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) mode_option = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* Cleanup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static void __exit s3fb_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pr_debug("s3fb: cleaning up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) pci_unregister_driver(&s3fb_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* Driver Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static int __init s3fb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (fb_get_options("s3fb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) s3fb_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) pr_debug("s3fb: initializing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return pci_register_driver(&s3fb_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Modularization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) module_init(s3fb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) module_exit(s3fb_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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