^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* drivers/video/s1d13xxxfb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (c) 2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Driver for Epson S1D13xxx series framebuffer chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Adapted from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * linux/drivers/video/skeletonfb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * linux/drivers/video/epson1355fb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * TODO: - handle dual screen display (CRT and LCD at the same time).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - check_var(), mode change, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - probably not SMP safe :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - support all bitblt operations on all cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * License. See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <video/s1d13xxxfb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PFX "s1d13xxxfb: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BLIT "s1d13xxxfb_bitblt: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * set this to enable debugging on general functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define dbg(fmt, args...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * set this to enable debugging on 2D acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define dbg_blit(fmt, args...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * we make sure only one bitblt operation is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * list of card production ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const int s1d13xxxfb_prod_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) S1D13505_PROD_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) S1D13506_PROD_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) S1D13806_PROD_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * List of card strings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char *s1d13xxxfb_prod_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "S1D13505",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "S1D13506",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "S1D13806",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * here we define the default struct fb_fix_screeninfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct fb_fix_screeninfo s1d13xxxfb_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .id = S1D_FBID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .visual = FB_VISUAL_PSEUDOCOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .xpanstep = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .ypanstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .ywrapstep = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .accel = FB_ACCEL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return readb(par->regs + regno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writeb(value, par->regs + regno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct s1d13xxxfb_regval *initregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if ((initregs[i].addr == S1DREG_DELAYOFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (initregs[i].addr == S1DREG_DELAYON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mdelay((int)initregs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* make sure the hardware can cope with us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) lcd_enable(struct s1d13xxxfb_par *par, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mode |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mode &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) crt_enable(struct s1d13xxxfb_par *par, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mode |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mode &= ~0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) framebuffer control functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) info->var.red.length = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) info->var.green.length = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) info->var.blue.length = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) s1d13xxxfb_setup_truecolour(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) info->fix.visual = FB_VISUAL_TRUECOLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) info->var.bits_per_pixel = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) info->var.red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) info->var.red.offset = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) info->var.green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) info->var.green.offset = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) info->var.blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) info->var.blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * s1d13xxxfb_set_par - Alters the hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @info: frame buffer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Using the fb_var_screeninfo in fb_info we set the depth of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * framebuffer. This function alters the par AND the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * fb_info since we are using that data. This means we depend on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * data in var inside fb_info to be supported by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * xxxfb_check_var is always called before xxxfb_set_par to ensure this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * XXX TODO: write proper s1d13xxxfb_check_var(), without which that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * function is quite useless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) s1d13xxxfb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct s1d13xxxfb_par *s1dfb = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if ((s1dfb->display & 0x01)) /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else /* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) switch (info->var.bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dbg("pseudo colour 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) s1d13xxxfb_setup_pseudocolour(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dbg("pseudo colour 8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) s1d13xxxfb_setup_pseudocolour(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val |= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dbg("true colour\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) s1d13xxxfb_setup_truecolour(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val |= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dbg("bpp not supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dbg("writing %02x to display mode register\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((s1dfb->display & 0x01)) /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else /* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) info->fix.line_length /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dbg("setting line_length to %d\n", info->fix.line_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dbg("done setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * s1d13xxxfb_setcolreg - sets a color register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @regno: Which register in the CLUT we are programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @red: The red value which can be up to 16 bits wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @green: The green value which can be up to 16 bits wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @blue: The blue value which can be up to 16 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @transp: If supported the alpha value which can be up to 16 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @info: frame buffer info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Returns negative errno on error, or zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u_int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct s1d13xxxfb_par *s1dfb = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int pseudo_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (regno >= S1D_PALETTE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) regno, red, green, blue, transp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (info->var.grayscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (info->fix.visual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case FB_VISUAL_TRUECOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (regno >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* deal with creating pseudo-palette entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pseudo_val = (red >> 11) << info->var.red.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pseudo_val |= (green >> 10) << info->var.green.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pseudo_val |= (blue >> 11) << info->var.blue.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regno, pseudo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ((u32 *)info->pseudo_palette)[regno] = pseudo_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case FB_VISUAL_PSEUDOCOLOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dbg("s1d13xxxfb_setcolreg: done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * s1d13xxxfb_blank - blanks the display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @blank_mode: the blank mode we want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @info: frame buffer structure that represents a single frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Blank the screen if blank_mode != 0, else unblank. Return 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * video mode which doesn't support it. Implements VESA suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * and powerdown modes on hardware that supports disabling hsync/vsync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * blank_mode == 2: suspend vsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * blank_mode == 3: suspend hsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * blank_mode == 4: powerdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Returns negative errno on error, or zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct s1d13xxxfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) switch (blank_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case FB_BLANK_UNBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case FB_BLANK_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if ((par->display & 0x01) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) lcd_enable(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if ((par->display & 0x02) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) crt_enable(par, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case FB_BLANK_VSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case FB_BLANK_HSYNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case FB_BLANK_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) lcd_enable(par, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) crt_enable(par, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* let fbcon do a soft blank for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * s1d13xxxfb_pan_display - Pans the display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @var: frame buffer variable screen structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @info: frame buffer structure that represents a single frame buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Pan (or wrap, depending on the `vmode' field) the display using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * `yoffset' field of the `var' structure (`xoffset' not yet supported).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * If the values don't fit, return -EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Returns negative errno on error, or zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct s1d13xxxfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (var->xoffset != 0) /* not yet ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (var->yoffset + info->var.yres > info->var.yres_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) start = (info->fix.line_length >> 1) * var->yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if ((par->display & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) functions to handle bitblt acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * bltbit_wait_bitclear - waits for change in register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * @info : frambuffer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * @bit : value currently in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @timeout : ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * waits until value changes FROM bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dbg_blit("wait_bitclear timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * @info : framebuffer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * @area : fb_copyarea structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * supports (atleast) S1D13506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 dst, src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u16 reverse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 sx = area->sx, sy = area->sy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u16 dx = area->dx, dy = area->dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u16 width = area->width, height = area->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u16 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) spin_lock(&s1d13xxxfb_bitblt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* bytes per xres line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bpp = (info->var.bits_per_pixel >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) stride = bpp * info->var.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* reverse, calculate the last pixel in rectangle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reverse = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* not reverse, calculate the first pixel in rectangle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else { /* (y * xres) + (bpp * x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dst = (dy * stride) + (bpp * dx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) src = (sy * stride) + (bpp * sx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* set source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* set destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* program height and width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* negative direction ROP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (reverse == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dbg_blit("(copyarea) negative rop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else /* positive direction ROP */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dbg_blit("(copyarea) positive rop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* set for rectangel mode and not linear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* setup the bpp 1 = 16bpp, 0 = 8bpp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* set words per xres */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dbg_blit("(copyarea) stride=%d\n", stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) (stride >> 1) & 0xff, stride >> 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* initialize the engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* wait to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bltbit_wait_bitclear(info, 0x80, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) spin_unlock(&s1d13xxxfb_bitblt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @info : framebuffer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * @rect : fb_fillrect structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * supports (atleast 13506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 screen_stride, dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 fg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u16 bpp = (info->var.bits_per_pixel >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* grab spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spin_lock(&s1d13xxxfb_bitblt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* bytes per x width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) screen_stride = (bpp * info->var.xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* bytes to starting point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) "(solidfill) : rect_width=%d, rect_height=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) rect->dx, rect->dy, screen_stride, dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rect->width - 1, rect->height - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) info->var.xres, info->var.yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dbg_blit("(solidfill) : rop=%d\n", rect->rop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* We split the destination into the three registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* give information regarding rectangel width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* give information regarding rectangel height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) fg = ((u32 *)info->pseudo_palette)[rect->color];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dbg_blit("(solidfill) truecolor/directcolor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fg = rect->color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dbg_blit("(solidfill) color = %d\n", rect->color);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* set foreground color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* set rectangual region of memory (rectangle and not linear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* set operation mode SOLID_FILL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* set the memory offset for the bblt in word sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* and away we go.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* wait until its done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bltbit_wait_bitclear(info, 0x80, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* let others play */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) spin_unlock(&s1d13xxxfb_bitblt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* framebuffer information structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct fb_ops s1d13xxxfb_fbops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .fb_set_par = s1d13xxxfb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .fb_setcolreg = s1d13xxxfb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .fb_blank = s1d13xxxfb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .fb_pan_display = s1d13xxxfb_pan_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* gets replaced at chip detection time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int s1d13xxxfb_width_tab[2][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {4, 8, 16, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {9, 12, 18, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * hardware setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * @info: frame buffer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * We setup the framebuffer structures according to the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * hardware setup. On some machines, the BIOS will have filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * the chip registers with such info, on others, these values will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * have been written in some init procedure. In any case, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * software values needs to match the hardware ones. This is what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * this function ensures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Note: some of the hardcoded values here might need some love to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * work on various chips, and might need to no longer be hardcoded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static void s1d13xxxfb_fetch_hw_state(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct fb_fix_screeninfo *fix = &info->fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct s1d13xxxfb_par *par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 panel, display;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 xres, yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 xres_virtual, yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int bpp, lcd_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int is_color, is_dual, is_tft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int lcd_enabled, crt_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fix->type = FB_TYPE_PACKED_PIXELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* general info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) crt_enabled = (par->display & 0x02) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) lcd_enabled = (par->display & 0x01) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (lcd_enabled && crt_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (lcd_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) else /* CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bpp = display & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) switch (bpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case 2: /* 4 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case 3: /* 8 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) var->bits_per_pixel = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) var->red.offset = var->green.offset = var->blue.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) var->red.length = var->green.length = var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case 5: /* 16 bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) s1d13xxxfb_setup_truecolour(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dbg("bpp: %i\n", bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fb_alloc_cmap(&info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* LCD info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) is_color = (panel & 0x04) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) is_dual = (panel & 0x02) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) is_tft = (panel & 0x01) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (lcd_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else { /* crt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) xres_virtual = offset * 16 / var->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) yres_virtual = fix->smem_len / (offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) var->xres = xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) var->yres = yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) var->xres_virtual = xres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) var->yres_virtual = yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) var->xoffset = var->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) fix->line_length = offset * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) var->grayscale = !is_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) var->activate = FB_ACTIVATE_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dbg(PFX "bpp=%d, lcd_bpp=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "crt_enabled=%d, lcd_enabled=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "is_color=%d, is_dual=%d, is_tft=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void __s1d13xxxfb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct fb_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct s1d13xxxfb_par *par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (par && par->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* disable output & enable powersave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) iounmap(par->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) fb_dealloc_cmap(&info->cmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) iounmap(info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) framebuffer_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) release_mem_region(pdev->resource[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) resource_size(&pdev->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) release_mem_region(pdev->resource[1].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) resource_size(&pdev->resource[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int s1d13xxxfb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct fb_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unregister_framebuffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __s1d13xxxfb_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int s1d13xxxfb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct s1d13xxxfb_par *default_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct fb_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct s1d13xxxfb_pdata *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u8 revision, prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dbg("probe called: device is %p\n", pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* enable platform-dependent hardware glue, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (dev_get_platdata(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (pdata && pdata->platform_init_video)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pdata->platform_init_video();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (pdev->num_resources != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_err(&pdev->dev, "invalid num_resources: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pdev->num_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* resource[0] is VRAM, resource[1] is registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (pdev->resource[0].flags != IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) || pdev->resource[1].flags != IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(&pdev->dev, "invalid resource type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!request_mem_region(pdev->resource[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) resource_size(&pdev->resource[0]), "s1d13xxxfb mem")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_dbg(&pdev->dev, "request_mem_region failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!request_mem_region(pdev->resource[1].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) resource_size(&pdev->resource[1]), "s1d13xxxfb regs")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_dbg(&pdev->dev, "request_mem_region failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default_par = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) default_par->regs = ioremap(pdev->resource[1].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) resource_size(&pdev->resource[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!default_par->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) printk(KERN_ERR PFX "unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) info->pseudo_palette = default_par->pseudo_palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) info->screen_base = ioremap(pdev->resource[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) resource_size(&pdev->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) printk(KERN_ERR PFX "unable to map framebuffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* production id is top 6 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* revision id is lower 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (prod_id == s1d13xxxfb_prod_ids[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* looks like we got it in our list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) default_par->prod_id = prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) default_par->revision = revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) printk(KERN_INFO PFX "chip production id %i = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) prod_id, s1d13xxxfb_prod_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) printk(KERN_INFO PFX "chip revision %i\n", revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) printk(KERN_INFO PFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "unknown chip production id %i, revision %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) prod_id, revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) printk(KERN_INFO PFX "please contact maintainer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) info->fix = s1d13xxxfb_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) info->fix.mmio_start = pdev->resource[1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) info->fix.mmio_len = resource_size(&pdev->resource[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) info->fix.smem_start = pdev->resource[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) info->fix.smem_len = resource_size(&pdev->resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) default_par->regs, info->fix.smem_len / 1024, info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) info->par = default_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) info->fbops = &s1d13xxxfb_fbops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) switch(prod_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case S1D13506_PROD_ID: /* activate acceleration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* perform "manual" chip initialization, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (pdata && pdata->initregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) s1d13xxxfb_fetch_hw_state(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (register_framebuffer(info) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) fb_info(info, "%s frame buffer device\n", info->fix.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) __s1d13xxxfb_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct fb_info *info = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct s1d13xxxfb_par *s1dfb = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct s1d13xxxfb_pdata *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* disable display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) lcd_enable(s1dfb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) crt_enable(s1dfb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (dev_get_platdata(&dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pdata = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!s1dfb->disp_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!s1dfb->disp_save) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) printk(KERN_ERR PFX "no memory to save screen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) s1dfb->disp_save = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!s1dfb->regs_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!s1dfb->regs_save) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) printk(KERN_ERR PFX "no memory to save registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* backup all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* now activate power save mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (pdata && pdata->platform_suspend_video)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return pdata->platform_suspend_video();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int s1d13xxxfb_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct fb_info *info = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct s1d13xxxfb_par *s1dfb = info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct s1d13xxxfb_pdata *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* awaken the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* do not let go until SDRAM "wakes up" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (dev_get_platdata(&dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) pdata = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (s1dfb->regs_save) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* will write RO regs, *should* get away with it :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) kfree(s1dfb->regs_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (s1dfb->disp_save) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) memcpy_toio(info->screen_base, s1dfb->disp_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) info->fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if ((s1dfb->display & 0x01) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) lcd_enable(s1dfb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if ((s1dfb->display & 0x02) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) crt_enable(s1dfb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (pdata && pdata->platform_resume_video)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return pdata->platform_resume_video();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static struct platform_driver s1d13xxxfb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .probe = s1d13xxxfb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .remove = s1d13xxxfb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .suspend = s1d13xxxfb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .resume = s1d13xxxfb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .name = S1D_DEVICENAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) s1d13xxxfb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (fb_get_options("s1d13xxxfb", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return platform_driver_register(&s1d13xxxfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) s1d13xxxfb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) platform_driver_unregister(&s1d13xxxfb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) module_init(s1d13xxxfb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) module_exit(s1d13xxxfb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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