Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __RIVAFB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __RIVAFB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "riva_hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* GGI compatibility macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NUM_SEQ_REGS		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NUM_CRT_REGS		0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NUM_GRC_REGS		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NUM_ATC_REGS		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DDC_SCL_READ_MASK       (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DDC_SCL_WRITE_MASK      (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDC_SDA_READ_MASK       (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DDC_SDA_WRITE_MASK      (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * From KGI originally. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct riva_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u8 attr[NUM_ATC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u8 crtc[NUM_CRT_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u8 gra[NUM_GRC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u8 seq[NUM_SEQ_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u8 misc_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	RIVA_HW_STATE ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct riva_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct riva_i2c_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	struct riva_par *par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned long   ddc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct i2c_algo_bit_data algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct riva_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	RIVA_HW_INST riva;	/* interface to riva_hw.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u32 pseudo_palette[16]; /* default palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u32 palette[16];        /* for Riva128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	u8 __iomem *ctrl_base;	/* virtual control register base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	unsigned dclk_max;	/* max DCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	struct riva_regs initial_state;	/* initial startup video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct riva_regs current_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	struct vgastate state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	struct mutex open_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	unsigned int ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	unsigned char *EDID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	unsigned int Chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	int forceCRTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	Bool SecondCRTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	int FlatPanel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	int cursor_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	int wc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	struct riva_i2c_chan chan[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void riva_common_setup(struct riva_par *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long riva_get_memlen(struct riva_par *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long riva_get_maxdclk(struct riva_par *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void riva_delete_i2c_busses(struct riva_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void riva_create_i2c_busses(struct riva_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif /* __RIVAFB_H */