^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on radeonfb-i2c.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "rivafb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../edid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void riva_gpio_setscl(void* data, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct riva_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct riva_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) val |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) val &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void riva_gpio_setsda(void* data, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct riva_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct riva_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int riva_gpio_getscl(void* data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct riva_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct riva_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int riva_gpio_getsda(void* data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct riva_i2c_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct riva_par *par = chan->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int i2c_class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) strcpy(chan->adapter.name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) chan->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) chan->adapter.class = i2c_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) chan->adapter.algo_data = &chan->algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) chan->adapter.dev.parent = &chan->par->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) chan->algo.setsda = riva_gpio_setsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) chan->algo.setscl = riva_gpio_setscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) chan->algo.getsda = riva_gpio_getsda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) chan->algo.getscl = riva_gpio_getscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) chan->algo.udelay = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) chan->algo.timeout = msecs_to_jiffies(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) chan->algo.data = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) i2c_set_adapdata(&chan->adapter, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Raise SCL and SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) riva_gpio_setsda(chan, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) riva_gpio_setscl(chan, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rc = i2c_bit_add_bus(&chan->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_warn(&chan->par->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "Failed to register I2C bus %s.\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) chan->par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void riva_create_i2c_busses(struct riva_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) par->chan[0].par = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) par->chan[1].par = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) par->chan[2].par = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) par->chan[0].ddc_base = 0x36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) par->chan[1].ddc_base = 0x3e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) par->chan[2].ddc_base = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) riva_setup_i2c_bus(&par->chan[0], "BUS1", I2C_CLASS_HWMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) riva_setup_i2c_bus(&par->chan[1], "BUS2", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) riva_setup_i2c_bus(&par->chan[2], "BUS3", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void riva_delete_i2c_busses(struct riva_par *par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!par->chan[i].par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) i2c_del_adapter(&par->chan[i].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) par->chan[i].par = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 *edid = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (par->chan[conn].par)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) edid = fb_ddc_read(&par->chan[conn].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (out_edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *out_edid = edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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