Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 1996-1997  David J. McKay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifndef __NVREG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define __NVREG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Little macro to construct bitmask for contiguous ranges of bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1)  << (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Macro to set specific bitfields (mask has to be a macro x:y) ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SetBF(mask,value) ((value) << (0?mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)                                              | SetBF(mask,value)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DEVICE_BASE(device) (0?NV##_##device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* This is where we will have to have conditional compilation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DEVICE_ACCESS(device,reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)   nvCONTROL[(NV_##device##_##reg)/4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DEVICE_READ(device,reg)        DEVICE_ACCESS(device,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DEVICE_PRINT(device,reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)   ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DEVICE_DEF(device,mask,value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)   SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PDAC_Write(reg,value)           DEVICE_WRITE(PDAC,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PDAC_Read(reg)                  DEVICE_READ(PDAC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PDAC_Print(reg)                 DEVICE_PRINT(PDAC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PDAC_Def(mask,value)            DEVICE_DEF(PDAC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PDAC_Val(mask,value)            DEVICE_VALUE(PDAC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PDAC_Mask(mask)                 DEVICE_MASK(PDAC,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PFB_Write(reg,value)            DEVICE_WRITE(PFB,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PFB_Read(reg)                   DEVICE_READ(PFB,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PFB_Print(reg)                  DEVICE_PRINT(PFB,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PFB_Def(mask,value)             DEVICE_DEF(PFB,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PFB_Val(mask,value)             DEVICE_VALUE(PFB,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PFB_Mask(mask)                  DEVICE_MASK(PFB,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PRM_Write(reg,value)            DEVICE_WRITE(PRM,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PRM_Read(reg)                   DEVICE_READ(PRM,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PRM_Print(reg)                  DEVICE_PRINT(PRM,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PRM_Def(mask,value)             DEVICE_DEF(PRM,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PRM_Val(mask,value)             DEVICE_VALUE(PRM,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PRM_Mask(mask)                  DEVICE_MASK(PRM,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PGRAPH_Write(reg,value)         DEVICE_WRITE(PGRAPH,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PGRAPH_Read(reg)                DEVICE_READ(PGRAPH,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PGRAPH_Print(reg)               DEVICE_PRINT(PGRAPH,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PGRAPH_Def(mask,value)          DEVICE_DEF(PGRAPH,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PGRAPH_Val(mask,value)          DEVICE_VALUE(PGRAPH,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PGRAPH_Mask(mask)               DEVICE_MASK(PGRAPH,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PDMA_Write(reg,value)           DEVICE_WRITE(PDMA,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PDMA_Read(reg)                  DEVICE_READ(PDMA,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PDMA_Print(reg)                 DEVICE_PRINT(PDMA,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PDMA_Def(mask,value)            DEVICE_DEF(PDMA,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PDMA_Val(mask,value)            DEVICE_VALUE(PDMA,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PDMA_Mask(mask)                 DEVICE_MASK(PDMA,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define PTIMER_Write(reg,value)         DEVICE_WRITE(PTIMER,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define PTIMER_Read(reg)                DEVICE_READ(PTIMER,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PTIMER_Print(reg)               DEVICE_PRINT(PTIMER,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PTIMER_Def(mask,value)          DEVICE_DEF(PTIMER,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PTIMER_Val(mask,value)          DEVICE_VALUE(PTIEMR,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PTIMER_Mask(mask)               DEVICE_MASK(PTIMER,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PEXTDEV_Write(reg,value)         DEVICE_WRITE(PEXTDEV,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PEXTDEV_Read(reg)                DEVICE_READ(PEXTDEV,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PEXTDEV_Print(reg)               DEVICE_PRINT(PEXTDEV,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PEXTDEV_Def(mask,value)          DEVICE_DEF(PEXTDEV,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PEXTDEV_Val(mask,value)          DEVICE_VALUE(PEXTDEV,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PEXTDEV_Mask(mask)               DEVICE_MASK(PEXTDEV,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PFIFO_Write(reg,value)          DEVICE_WRITE(PFIFO,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PFIFO_Read(reg)                 DEVICE_READ(PFIFO,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PFIFO_Print(reg)                DEVICE_PRINT(PFIFO,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PFIFO_Def(mask,value)           DEVICE_DEF(PFIFO,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PFIFO_Val(mask,value)           DEVICE_VALUE(PFIFO,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PFIFO_Mask(mask)                DEVICE_MASK(PFIFO,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PRAM_Write(reg,value)           DEVICE_WRITE(PRAM,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PRAM_Read(reg)                  DEVICE_READ(PRAM,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PRAM_Print(reg)                 DEVICE_PRINT(PRAM,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PRAM_Def(mask,value)            DEVICE_DEF(PRAM,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PRAM_Val(mask,value)            DEVICE_VALUE(PRAM,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PRAM_Mask(mask)                 DEVICE_MASK(PRAM,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PRAMFC_Write(reg,value)         DEVICE_WRITE(PRAMFC,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PRAMFC_Read(reg)                DEVICE_READ(PRAMFC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PRAMFC_Print(reg)               DEVICE_PRINT(PRAMFC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PRAMFC_Def(mask,value)          DEVICE_DEF(PRAMFC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PRAMFC_Val(mask,value)          DEVICE_VALUE(PRAMFC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PRAMFC_Mask(mask)               DEVICE_MASK(PRAMFC,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PMC_Write(reg,value)            DEVICE_WRITE(PMC,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PMC_Read(reg)                   DEVICE_READ(PMC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PMC_Print(reg)                  DEVICE_PRINT(PMC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PMC_Def(mask,value)             DEVICE_DEF(PMC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PMC_Val(mask,value)             DEVICE_VALUE(PMC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PMC_Mask(mask)                  DEVICE_MASK(PMC,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PMC_Write(reg,value)            DEVICE_WRITE(PMC,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PMC_Read(reg)                   DEVICE_READ(PMC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PMC_Print(reg)                  DEVICE_PRINT(PMC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PMC_Def(mask,value)             DEVICE_DEF(PMC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PMC_Val(mask,value)             DEVICE_VALUE(PMC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PMC_Mask(mask)                  DEVICE_MASK(PMC,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PBUS_Write(reg,value)         DEVICE_WRITE(PBUS,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PBUS_Read(reg)                DEVICE_READ(PBUS,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PBUS_Print(reg)               DEVICE_PRINT(PBUS,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PBUS_Def(mask,value)          DEVICE_DEF(PBUS,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PBUS_Val(mask,value)          DEVICE_VALUE(PBUS,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PBUS_Mask(mask)               DEVICE_MASK(PBUS,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PRAMDAC_Write(reg,value)         DEVICE_WRITE(PRAMDAC,reg,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PRAMDAC_Read(reg)                DEVICE_READ(PRAMDAC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PRAMDAC_Print(reg)               DEVICE_PRINT(PRAMDAC,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PRAMDAC_Def(mask,value)          DEVICE_DEF(PRAMDAC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PRAMDAC_Val(mask,value)          DEVICE_VALUE(PRAMDAC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PRAMDAC_Mask(mask)               DEVICE_MASK(PRAMDAC,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PDAC_ReadExt(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)   ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)   (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)   (PDAC_Read(INDEX_DATA)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PDAC_WriteExt(reg,value)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)   ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)   (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)   (PDAC_Write(INDEX_DATA,(value))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCRTC_Def(mask,value)          DEVICE_DEF(PCRTC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCRTC_Val(mask,value)          DEVICE_VALUE(PCRTC,mask,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCRTC_Mask(mask)               DEVICE_MASK(PCRTC,mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) extern volatile unsigned  *nvCONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NVChipType GetChipType(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)