^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef __PXAFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define __PXAFB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * linux/drivers/video/pxafb.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * -- Intel PXA250/210 LCD Controller Frame Buffer Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999 Eric A. Thomas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2004 Jean-Frederic Clere.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004 Ian Campbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2004 Jeff Lackey.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * which in turn is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Based on acornfb.c Copyright (C) Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 2001-08-03: Cliff Brake <cbrake@acclent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - ported SA1100 code to PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PXA LCD DMA descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct pxafb_dma_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int fdadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int fsadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int fidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int ldcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PAL_NONE = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PAL_BASE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PAL_OV1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PAL_OV2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PAL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DMA_BASE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DMA_UPPER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DMA_LOWER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DMA_OV1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DMA_OV2_Y = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DMA_OV2_Cb = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DMA_OV2_Cr = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DMA_CURSOR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DMA_CMD = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DMA_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* maximum palette size - 256 entries, each 4 bytes long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PALETTE_SIZE (256 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CMD_BUFF_SIZE (1024 * 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* NOTE: the palette and frame dma descriptors are doubled to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * the 2nd set for branch settings (FBRx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pxafb_dma_buff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char palette[PAL_MAX * PALETTE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) uint16_t cmd_buff[CMD_BUFF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OVERLAY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OVERLAY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) OVERLAY_FORMAT_RGB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) OVERLAY_FORMAT_YUV444_PACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) OVERLAY_FORMAT_YUV444_PLANAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) OVERLAY_FORMAT_YUV422_PLANAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) OVERLAY_FORMAT_YUV420_PLANAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pxafb_layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pxafb_layer_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void (*enable)(struct pxafb_layer *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void (*disable)(struct pxafb_layer *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void (*setup)(struct pxafb_layer *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct pxafb_layer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct fb_info fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uint32_t usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) uint32_t control[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pxafb_layer_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *video_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long video_mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) size_t video_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct completion branch_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pxafb_info *fbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pxafb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct fb_info fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct pxafb_dma_buff *dma_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) size_t dma_buff_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dma_addr_t dma_buff_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dma_addr_t fdadr[DMA_MAX * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __iomem *video_mem; /* virtual address of frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long video_mem_phys; /* physical address of frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_t video_mem_size; /* size of the frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 * palette_cpu; /* virtual address of palette memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u_int palette_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u_int lccr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u_int lccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u_int lccr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u_int cmap_inverse:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cmap_static:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unused:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u_int reg_lccr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u_int reg_lccr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u_int reg_lccr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u_int reg_lccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u_int reg_lccr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u_int reg_cmdcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long hsync_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) volatile u_char state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) volatile u_char task_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mutex ctrlr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) wait_queue_head_t ctrlr_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct work_struct task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct completion disable_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_FB_PXA_SMARTPANEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint16_t *smart_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) size_t n_smart_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct completion command_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct completion refresh_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct task_struct *smart_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #ifdef CONFIG_FB_PXA_OVERLAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pxafb_layer overlay[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct notifier_block freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct regulator *lcd_supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool lcd_supply_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void (*lcd_power)(int, struct fb_var_screeninfo *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void (*backlight_power)(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pxafb_mach_info *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * These are the actions for set_ctrlr_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define C_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define C_ENABLE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define C_DISABLE_CLKCHANGE (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define C_ENABLE_CLKCHANGE (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define C_REENABLE (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define C_DISABLE_PM (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define C_ENABLE_PM (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define C_STARTUP (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PXA_NAME "PXA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Minimum X and Y resolutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MIN_XRES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MIN_YRES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* maximum X and Y resolutions - note these are limits from the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * bits length instead of the real ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MAX_XRES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MAX_YRES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif /* __PXAFB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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