Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __PXA3XX_GCU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __PXA3XX_GCU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /* Number of 32bit words in display list (ring buffer). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define PXA3XX_GCU_BUFFER_WORDS  ((256 * 1024 - 256) / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* To be increased when breaking the ABI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PXA3XX_GCU_SHARED_MAGIC  0x30000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PXA3XX_GCU_BATCH_WORDS   8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct pxa3xx_gcu_shared {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	u32            buffer[PXA3XX_GCU_BUFFER_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	bool           hw_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	unsigned long  buffer_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned int   num_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	unsigned int   num_writes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	unsigned int   num_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	unsigned int   num_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	unsigned int   num_wait_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	unsigned int   num_wait_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	unsigned int   num_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u32            magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Initialization and synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * Hardware is started upon write(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PXA3XX_GCU_IOCTL_RESET		_IO('G', 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PXA3XX_GCU_IOCTL_WAIT_IDLE	_IO('G', 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif /* __PXA3XX_GCU_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)