^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __PXA168FB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __PXA168FB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* ------------< LCD register >------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* Video Frame 0&1 start address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* YC & UV Pitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LCD_SPU_DMA_PITCH_YC 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPU_DMA_PITCH_C(c) ((c) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPU_DMA_PITCH_Y(y) (y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LCD_SPU_DMA_PITCH_UV 0x00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPU_DMA_PITCH_V(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPU_DMA_PITCH_U(u) (u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Video Starting Point on Screen Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Video Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LCD_SPU_DMA_HPXL_VLN 0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CFG_DMA_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CFG_DMA_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Video Size After zooming Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LCD_SPU_DZM_HPXL_VLN 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CFG_DZM_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CFG_DZM_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Graphic Frame 0&1 Starting Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LCD_CFG_GRA_START_ADDR0 0x00F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LCD_CFG_GRA_START_ADDR1 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Graphic Frame Pitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LCD_CFG_GRA_PITCH 0x00FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Graphic Starting Point on Screen Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CFG_GRA_OVSA_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CFG_GRA_OVSA_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Graphic Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LCD_SPU_GRA_HPXL_VLN 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CFG_GRA_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CFG_GRA_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Graphic Size after Zooming Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LCD_SPU_GZM_HPXL_VLN 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CFG_GZM_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CFG_GZM_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* HW Cursor Starting Point on Screen Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CFG_HWC_OVSA_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CFG_HWC_OVSA_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* HW Cursor Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LCD_SPU_HWC_HPXL_VLN 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CFG_HWC_VLN(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CFG_HWC_HPXL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Total Screen Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LCD_SPUT_V_H_TOTAL 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CFG_V_TOTAL(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CFG_H_TOTAL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Total Screen Active Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LCD_SPU_V_H_ACTIVE 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CFG_V_ACTIVE(y) ((y) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CFG_H_ACTIVE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Screen H&V Porch Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LCD_SPU_H_PORCH 0x011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CFG_H_BACK_PORCH(b) ((b) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CFG_H_FRONT_PORCH(f) (f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LCD_SPU_V_PORCH 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CFG_V_BACK_PORCH(b) ((b) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CFG_V_FRONT_PORCH(f) (f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Screen Blank Color Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LCD_SPU_BLANKCOLOR 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CFG_BLANKCOLOR_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CFG_BLANKCOLOR_R_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CFG_BLANKCOLOR_G_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CFG_BLANKCOLOR_B_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* HW Cursor Color 1&2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LCD_SPU_ALPHA_COLOR1 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CFG_HWC_COLOR1 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CFG_HWC_COLOR1_R(red) ((red) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CFG_HWC_COLOR1_G(green) ((green) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CFG_HWC_COLOR1_B(blue) (blue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CFG_HWC_COLOR1_R_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CFG_HWC_COLOR1_G_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CFG_HWC_COLOR1_B_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LCD_SPU_ALPHA_COLOR2 0x012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CFG_HWC_COLOR2 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CFG_HWC_COLOR2_R_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CFG_HWC_COLOR2_G_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CFG_HWC_COLOR2_B_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Video YUV Color Key Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LCD_SPU_COLORKEY_Y 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CFG_CKEY_Y2(y2) ((y2) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CFG_CKEY_Y2_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CFG_CKEY_Y1(y1) ((y1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CFG_CKEY_Y1_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CFG_CKEY_Y(y) ((y) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CFG_CKEY_Y_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CFG_ALPHA_Y(y) (y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CFG_ALPHA_Y_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LCD_SPU_COLORKEY_U 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CFG_CKEY_U2(u2) ((u2) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CFG_CKEY_U2_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CFG_CKEY_U1(u1) ((u1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CFG_CKEY_U1_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CFG_CKEY_U(u) ((u) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CFG_CKEY_U_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CFG_ALPHA_U(u) (u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CFG_ALPHA_U_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LCD_SPU_COLORKEY_V 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CFG_CKEY_V2(v2) ((v2) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CFG_CKEY_V2_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CFG_CKEY_V1(v1) ((v1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CFG_CKEY_V1_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CFG_CKEY_V(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CFG_CKEY_V_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CFG_ALPHA_V(v) (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CFG_ALPHA_V_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* SPI Read Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LCD_SPU_SPI_RXDATA 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Smart Panel Read Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LCD_SPU_ISA_RSDATA 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* HWC SRAM Read Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LCD_SPU_HWC_RDDAT 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Gamma Table SRAM Read Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LCD_SPU_GAMMA_RDDAT 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CFG_GAMMA_RDDAT_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Palette Table SRAM Read Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LCD_SPU_PALETTE_RDDAT 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* I/O Pads Input Read Only Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LCD_SPU_IOPAD_IN 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CFG_IOPAD_IN_MASK 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Reserved Read Only Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LCD_CFG_RDREG5F 0x017C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IRE_FRAME_CNT_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IPE_FRAME_CNT_MASK 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* SPI Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LCD_SPU_SPI_CTRL 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CFG_SCLKCNT_MASK 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CFG_RXBITS_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CFG_TXBITS_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CFG_CLKINV(clk) ((clk) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CFG_CLKINV_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CFG_KEEPXFER(transfer) ((transfer) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CFG_KEEPXFER_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CFG_RXBITSTO0(rx) ((rx) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CFG_RXBITSTO0_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CFG_TXBITSTO0(tx) ((tx) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CFG_TXBITSTO0_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CFG_SPI_ENA(spi) ((spi) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CFG_SPI_ENA_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CFG_SPI_SEL(spi) ((spi) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CFG_SPI_SEL_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CFG_SPI_3W4WB(wire) ((wire) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CFG_SPI_3W4WB_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CFG_SPI_START(start) (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CFG_SPI_START_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* SPI Tx Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LCD_SPU_SPI_TXDATA 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 1. Smart Pannel 8-bit Bus Control Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 2. AHB Slave Path Data Port Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define LCD_SPU_SMPN_CTRL 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* DMA Control 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LCD_SPU_DMA_CTRL0 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CFG_NOBLENDING(nb) ((nb) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CFG_NOBLENDING_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CFG_GAMMA_ENA(gn) ((gn) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CFG_GAMMA_ENA_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CFG_CBSH_ENA(cn) ((cn) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CFG_CBSH_ENA_MASK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CFG_PALETTE_ENA(pn) ((pn) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CFG_PALETTE_ENA_MASK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CFG_ARBFAST_ENA(an) ((an) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CFG_ARBFAST_ENA_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CFG_HWC_1BITMOD(mode) ((mode) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CFG_HWC_1BITMOD_MASK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CFG_HWC_1BITENA(mn) ((mn) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CFG_HWC_1BITENA_MASK 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CFG_HWC_ENA(cn) ((cn) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CFG_HWC_ENA_MASK 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CFG_DMAFORMAT(dmaformat) ((dmaformat) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CFG_DMAFORMAT_MASK 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CFG_GRAFORMAT(graformat) ((graformat) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CFG_GRAFORMAT_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* for graphic part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CFG_GRA_FTOGGLE(toggle) ((toggle) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CFG_GRA_FTOGGLE_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CFG_GRA_HSMOOTH(smooth) ((smooth) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CFG_GRA_HSMOOTH_MASK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CFG_GRA_TSTMODE(test) ((test) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CFG_GRA_TSTMODE_MASK 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CFG_GRA_SWAPRB(swap) ((swap) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CFG_GRA_SWAPRB_MASK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CFG_GRA_SWAPUV(swap) ((swap) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CFG_GRA_SWAPUV_MASK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CFG_GRA_SWAPYU(swap) ((swap) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CFG_GRA_SWAPYU_MASK 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CFG_YUV2RGB_GRA(cvrt) ((cvrt) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CFG_YUV2RGB_GRA_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CFG_GRA_ENA(gra) ((gra) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CFG_GRA_ENA_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* for video part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CFG_DMA_FTOGGLE(toggle) ((toggle) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CFG_DMA_FTOGGLE_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CFG_DMA_HSMOOTH(smooth) ((smooth) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CFG_DMA_HSMOOTH_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CFG_DMA_TSTMODE(test) ((test) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CFG_DMA_TSTMODE_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CFG_DMA_SWAPRB(swap) ((swap) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CFG_DMA_SWAPRB_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CFG_DMA_SWAPUV(swap) ((swap) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CFG_DMA_SWAPUV_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CFG_DMA_SWAPYU(swap) ((swap) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CFG_DMA_SWAPYU_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CFG_DMA_SWAP_MASK 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CFG_YUV2RGB_DMA(cvrt) ((cvrt) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CFG_YUV2RGB_DMA_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CFG_DMA_ENA(video) (video)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CFG_DMA_ENA_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* DMA Control 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LCD_SPU_DMA_CTRL1 0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CFG_FRAME_TRIG(trig) ((trig) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CFG_FRAME_TRIG_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CFG_VSYNC_TRIG(trig) ((trig) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CFG_VSYNC_TRIG_MASK 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CFG_VSYNC_INV(inv) ((inv) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CFG_VSYNC_INV_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CFG_COLOR_KEY_MODE(cmode) ((cmode) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CFG_COLOR_KEY_MASK 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CFG_CARRY(carry) ((carry) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CFG_CARRY_MASK 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CFG_LNBUF_ENA(lnbuf) ((lnbuf) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CFG_LNBUF_ENA_MASK 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CFG_GATED_ENA(gated) ((gated) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CFG_GATED_ENA_MASK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CFG_PWRDN_ENA(power) ((power) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CFG_PWRDN_ENA_MASK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CFG_DSCALE(dscale) ((dscale) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CFG_DSCALE_MASK 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CFG_ALPHA_MODE(amode) ((amode) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CFG_ALPHA_MODE_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CFG_ALPHA(alpha) ((alpha) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CFG_ALPHA_MASK 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CFG_PXLCMD(pxlcmd) (pxlcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CFG_PXLCMD_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* SRAM Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define LCD_SPU_SRAM_CTRL 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CFG_SRAM_INIT_WR_RD(mode) ((mode) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CFG_SRAM_ADDR_LCDID(id) ((id) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CFG_SRAM_ADDR(addr) (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CFG_SRAM_ADDR_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* SRAM Write Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define LCD_SPU_SRAM_WRDAT 0x019C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* SRAM RTC/WTC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define LCD_SPU_SRAM_PARA0 0x01A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* SRAM Power Down Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define LCD_SPU_SRAM_PARA1 0x01A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CFG_CSB_256x32_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CFG_CSB_256x24(palette) ((palette) << 14) /* Palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CFG_CSB_256x24_MASK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CFG_CSB_256x8(gamma) ((gamma) << 13) /* Gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CFG_CSB_256x8_MASK 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CFG_PDWN256x32(pdwn) ((pdwn) << 7) /* HWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CFG_PDWN256x32_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CFG_PDWN256x24(pdwn) ((pdwn) << 6) /* Palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CFG_PDWN256x24_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CFG_PDWN256x8(pdwn) ((pdwn) << 5) /* Gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CFG_PDWN256x8_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CFG_PDWN32x32(pdwn) ((pdwn) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CFG_PDWN32x32_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CFG_PDWN16x66(pdwn) ((pdwn) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CFG_PDWN16x66_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CFG_PDWN32x66(pdwn) ((pdwn) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CFG_PDWN32x66_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CFG_PDWN64x66(pdwn) (pdwn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CFG_PDWN64x66_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Smart or Dumb Panel Clock Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define LCD_CFG_SCLK_DIV 0x01A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SCLK_SOURCE_SELECT(src) ((src) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SCLK_SOURCE_SELECT_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_FRACDIV(frac) ((frac) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_FRACDIV_MASK 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_INT_DIV(div) (div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_INT_DIV_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Video Contrast Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define LCD_SPU_CONTRAST 0x01AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CFG_BRIGHTNESS(bright) ((bright) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CFG_BRIGHTNESS_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CFG_CONTRAST(contrast) (contrast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CFG_CONTRAST_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Video Saturation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define LCD_SPU_SATURATION 0x01B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CFG_C_MULTS(mult) ((mult) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CFG_C_MULTS_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CFG_SATURATION(sat) (sat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CFG_SATURATION_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Video Hue Adjust Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define LCD_SPU_CBSH_HUE 0x01B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CFG_SIN0(sin0) ((sin0) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CFG_SIN0_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CFG_COS0(con0) (con0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CFG_COS0_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Dump LCD Panel Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define LCD_SPU_DUMB_CTRL 0x01B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CFG_DUMBMODE(mode) ((mode) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CFG_DUMBMODE_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CFG_LCDGPIO_O(data) ((data) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CFG_LCDGPIO_O_MASK 0x0FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CFG_LCDGPIO_ENA(gpio) ((gpio) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CFG_LCDGPIO_ENA_MASK 0x000FF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CFG_BIAS_OUT(bias) ((bias) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CFG_BIAS_OUT_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CFG_REVERSE_RGB(rRGB) ((rRGB) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CFG_REVERSE_RGB_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CFG_INV_COMPBLANK(blank) ((blank) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CFG_INV_COMPBLANK_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CFG_INV_COMPSYNC(sync) ((sync) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CFG_INV_COMPSYNC_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CFG_INV_HENA(hena) ((hena) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CFG_INV_HENA_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CFG_INV_VSYNC(vsync) ((vsync) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CFG_INV_VSYNC_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CFG_INV_HSYNC(hsync) ((hsync) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CFG_INV_HSYNC_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CFG_INV_PCLK(pclk) ((pclk) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CFG_INV_PCLK_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CFG_DUMB_ENA(dumb) (dumb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CFG_DUMB_ENA_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* LCD I/O Pads Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SPU_IOPAD_CONTROL 0x01BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CFG_GRA_VM_ENA_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CFG_DMA_VM_ENA(vm) ((vm) << 13) /* video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CFG_DMA_VM_ENA_MASK 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CFG_CMD_VM_ENA(vm) ((vm) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CFG_CMD_VM_ENA_MASK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CFG_CSC(csc) ((csc) << 8) /* csc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CFG_CSC_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CFG_AXICTRL(axi) ((axi) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CFG_AXICTRL_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CFG_IOPADMODE(iopad) (iopad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CFG_IOPADMODE_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* LCD Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SPU_IRQ_ENA 0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DMA_FRAME_IRQ0_ENA(irq) ((irq) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DMA_FRAME_IRQ1_ENA(irq) ((irq) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DMA_FF_UNDERFLOW_ENA(ff) ((ff) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define GRA_FRAME_IRQ0_ENA(irq) ((irq) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define GRA_FRAME_IRQ1_ENA(irq) ((irq) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define GRA_FF_UNDERFLOW_ENA(ff) ((ff) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define VSYNC_IRQ_ENA_MASK 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DUMB_FRAMEDONE_ENA(fdone) ((fdone) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DUMB_FRAMEDONE_ENA_MASK 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define TWC_FRAMEDONE_ENA(fdone) ((fdone) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define TWC_FRAMEDONE_ENA_MASK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define HWC_FRAMEDONE_ENA(fdone) ((fdone) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HWC_FRAMEDONE_ENA_MASK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SLV_IRQ_ENA(irq) ((irq) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SLV_IRQ_ENA_MASK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SPI_IRQ_ENA(irq) ((irq) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SPI_IRQ_ENA_MASK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PWRDN_IRQ_ENA(irq) ((irq) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PWRDN_IRQ_ENA_MASK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define ERR_IRQ_ENA(irq) ((irq) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define ERR_IRQ_ENA_MASK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CLEAN_SPU_IRQ_ISR(irq) (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* LCD Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SPU_IRQ_ISR 0x01C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define DMA_FRAME_IRQ0(irq) ((irq) << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DMA_FRAME_IRQ0_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define DMA_FRAME_IRQ1(irq) ((irq) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define DMA_FRAME_IRQ1_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DMA_FF_UNDERFLOW(ff) ((ff) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define DMA_FF_UNDERFLOW_MASK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define GRA_FRAME_IRQ0(irq) ((irq) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define GRA_FRAME_IRQ0_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define GRA_FRAME_IRQ1(irq) ((irq) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define GRA_FRAME_IRQ1_MASK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define GRA_FF_UNDERFLOW(ff) ((ff) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define GRA_FF_UNDERFLOW_MASK 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define VSYNC_IRQ(vsync_irq) ((vsync_irq) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define VSYNC_IRQ_MASK 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DUMB_FRAMEDONE(fdone) ((fdone) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DUMB_FRAMEDONE_MASK 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TWC_FRAMEDONE(fdone) ((fdone) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TWC_FRAMEDONE_MASK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HWC_FRAMEDONE(fdone) ((fdone) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HWC_FRAMEDONE_MASK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SLV_IRQ(irq) ((irq) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SLV_IRQ_MASK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SPI_IRQ(irq) ((irq) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SPI_IRQ_MASK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PWRDN_IRQ(irq) ((irq) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PWRDN_IRQ_MASK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define ERR_IRQ(irq) ((irq) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define ERR_IRQ_MASK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define DMA_FRAME_CNT_ISR_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define GRA_FRAME_CNT_ISR_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define VSYNC_IRQ_LEVEL_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SLV_FF_EMPTY_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DMA_FF_ALLEMPTY_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define GRA_FF_ALLEMPTY_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define PWRDN_IRQ_LEVEL_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * defined Video Memory Color format for DMA control 0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * DMA0 bit[23:20]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define VMODE_RGB565 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define VMODE_RGB1555 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define VMODE_RGB888PACKED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define VMODE_RGB888UNPACKED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define VMODE_RGBA888 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define VMODE_YUV422PACKED 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define VMODE_YUV422PLANAR 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define VMODE_YUV420PLANAR 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define VMODE_SMPNCMD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define VMODE_PALETTE4BIT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define VMODE_PALETTE8BIT 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define VMODE_RESERVED 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * defined Graphic Memory Color format for DMA control 0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * DMA0 bit[19:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define GMODE_RGB565 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define GMODE_RGB1555 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define GMODE_RGB888PACKED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define GMODE_RGB888UNPACKED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define GMODE_RGBA888 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define GMODE_YUV422PACKED 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define GMODE_YUV422PLANAR 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define GMODE_YUV420PLANAR 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define GMODE_SMPNCMD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define GMODE_PALETTE4BIT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define GMODE_PALETTE8BIT 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define GMODE_RESERVED 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * define for DMA control 1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define DMA1_FRAME_TRIG 31 /* bit location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define DMA1_VSYNC_MODE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DMA1_VSYNC_INV 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define DMA1_CKEY 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define DMA1_CARRY 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define DMA1_LNBUF_ENA 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DMA1_GATED_ENA 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define DMA1_PWRDN_ENA 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define DMA1_DSCALE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DMA1_ALPHA_MODE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DMA1_ALPHA 08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DMA1_PXLCMD 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * defined for Configure Dumb Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * DUMB LCD Panel bit[31:28]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define DUMB16_RGB565_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DUMB16_RGB565_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DUMB18_RGB666_0 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DUMB18_RGB666_1 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DUMB12_RGB444_0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define DUMB12_RGB444_1 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DUMB24_RGB888_0 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define DUMB_BLANK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * defined for Configure I/O Pin Allocation Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * LCD LCD I/O Pads control register bit[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define IOPAD_DUMB24 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define IOPAD_DUMB18SPI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define IOPAD_DUMB18GPIO 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define IOPAD_DUMB16SPI 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define IOPAD_DUMB16GPIO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define IOPAD_DUMB12 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define IOPAD_SMART18SPI 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define IOPAD_SMART16SPI 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IOPAD_SMART8BOTH 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #endif /* __PXA168FB_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags