^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/video/pvr2fb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Dreamcast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2001 - 2008 Paul Mundt <lethal@linux-sh.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver is mostly based on the excellent amifb and vfb sources. It uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * an odd scheme for converting hardware values to/from framebuffer values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * here are some hacked-up formulas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The Dreamcast has screen offsets from each side of its four borders and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the start offsets of the display window. I used these values to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 'pseudo' values (think of them as placeholders) for the fb video mode, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * that when it came time to convert these values back into their hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * values, I could just add mode- specific offsets to get the correct mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * left_margin = diwstart_h - borderstart_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * right_margin = borderstop_h - (diwstart_h + xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * upper_margin = diwstart_v - borderstart_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * lower_margin = borderstop_v - (diwstart_h + yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * hsync_len = borderstart_h + (hsync_total - borderstop_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * vsync_len = borderstart_v + (vsync_total - borderstop_v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Then, when it's time to convert back to hardware settings, the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * constants are the borderstart_* offsets, all other values are derived from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * the fb video mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * // PAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * borderstart_h = 116;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * borderstart_v = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * borderstop_h = borderstart_h + hsync_total - hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * diwstart_v = borderstart_v - upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * However, in the current implementation, the borderstart values haven't had
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * the benefit of being fully researched, so some modes may be broken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_SH_DREAMCAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <mach-dreamcast/mach/sysasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef CONFIG_PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef CONFIG_SH_STORE_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <cpu/sq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifndef PCI_DEVICE_ID_NEC_NEON250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define PCI_DEVICE_ID_NEC_NEON250 0x0067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 2D video registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DISP_BASE par->mmio_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DISP_BRDRCOLR (DISP_BASE + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DISP_DIWMODE (DISP_BASE + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DISP_DIWADDRL (DISP_BASE + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DISP_DIWADDRS (DISP_BASE + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DISP_DIWSIZE (DISP_BASE + 0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DISP_SYNCCONF (DISP_BASE + 0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DISP_BRDRHORZ (DISP_BASE + 0xd4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DISP_SYNCSIZE (DISP_BASE + 0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DISP_BRDRVERT (DISP_BASE + 0xdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DISP_DIWCONF (DISP_BASE + 0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DISP_DIWHSTRT (DISP_BASE + 0xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DISP_DIWVSTRT (DISP_BASE + 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DISP_PIXDEPTH (DISP_BASE + 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Pixel clocks, one for TV output, doubled for VGA output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TV_CLK 74239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VGA_CLK 37119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PAL_HTOTAL 863
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PAL_VTOTAL 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NTSC_HTOTAL 857
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NTSC_VTOTAL 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Supported cable types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Supported video output types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum { VO_PAL, VO_NTSC, VO_VGA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Supported palette types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pvr2_params { unsigned int val; char *name; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct pvr2_params cables[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct pvr2_params outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * This describes the current video mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct pvr2fb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int hsync_total; /* Clocks/line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int vsync_total; /* Lines/field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int borderstart_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int borderstop_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int borderstart_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int borderstop_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int diwstart_h; /* Horizontal offset of the display field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int diwstart_v; /* Vertical offset of the display field, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) interlaced modes, this is the long field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long disp_start; /* Address of image within VRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned char is_interlaced; /* Is the display interlaced? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __iomem *mmio_base; /* MMIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } *currentpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct fb_info *fb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct fb_fix_screeninfo pvr2_fix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .id = "NEC PowerVR2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .type = FB_TYPE_PACKED_PIXELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .visual = FB_VISUAL_TRUECOLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ypanstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .ywrapstep = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .accel = FB_ACCEL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct fb_var_screeninfo pvr2_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .xres_virtual = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .yres_virtual = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .bits_per_pixel =16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .red = { 11, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .green = { 5, 6, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .blue = { 0, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .activate = FB_ACTIVATE_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .height = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .width = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .vmode = FB_VMODE_NONINTERLACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int cable_type = CT_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int video_output = VO_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int nopan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int nowrap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * We do all updating, blanking, etc. during the vertical retrace period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static unsigned int do_vmode_full = 0; /* Change the video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned int do_vmode_pan = 0; /* Update the video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static short do_blank = 0; /* (Un)Blank the screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static unsigned int is_blanked = 0; /* Is the screen blanked? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_SH_STORE_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static unsigned long pvr2fb_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned int shdma = PVR2_CASCADE_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct fb_videomode pvr2_modedb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * NTSC, so it shouldn't be a problem (I hope).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* 640x480 @ 60Hz interlaced (NTSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* 640x240 @ 60Hz (NTSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* XXX: Broken! Don't use... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FB_SYNC_BROADCAST, FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* 640x480 @ 60hz (VGA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0, FB_VMODE_YWRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DEFMODE_NTSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DEFMODE_PAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DEFMODE_VGA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int defmode = DEFMODE_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static char *mode_option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline void pvr2fb_set_pal_type(unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fb_writel(type, par->mmio_base + 0x108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int regno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int pvr2fb_blank(int blank, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) do_blank = blank ? blank : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline unsigned long get_line_length(int xres_virtual, int bpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void set_color_bitfields(struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (var->bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 16: /* RGB 565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pvr2fb_set_pal_type(PAL_RGB565);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) var->red.offset = 11; var->red.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) var->green.offset = 5; var->green.length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) var->blue.offset = 0; var->blue.length = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) var->transp.offset = 0; var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 24: /* RGB 888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) var->red.offset = 16; var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) var->green.offset = 8; var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) var->blue.offset = 0; var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) var->transp.offset = 0; var->transp.length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 32: /* ARGB 8888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pvr2fb_set_pal_type(PAL_ARGB8888);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) var->red.offset = 16; var->red.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) var->green.offset = 8; var->green.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) var->blue.offset = 0; var->blue.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) var->transp.offset = 24; var->transp.length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int green, unsigned int blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int transp, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (regno > info->cmap.len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * We only support the hardware palette for 16 and 32bpp. It's also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * expected that the palette format has been set by the time we get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * here, so we don't waste time setting it again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) switch (info->var.bits_per_pixel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case 16: /* RGB 565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tmp = (red & 0xf800) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ((green & 0xfc00) >> 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ((blue & 0xf800) >> 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pvr2fb_set_pal_entry(par, regno, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case 24: /* RGB 888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) red >>= 8; green >>= 8; blue >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tmp = (red << 16) | (green << 8) | blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 32: /* ARGB 8888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) red >>= 8; green >>= 8; blue >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pvr2fb_set_pal_entry(par, regno, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (regno < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ((u32*)(info->pseudo_palette))[regno] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Determine the cable type and initialize the cable output format. Don't do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * anything if the cable type has been overidden (via "cable:XX").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PCTRA ((void __iomem *)0xff80002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PDTRA ((void __iomem *)0xff800030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define VOUTC ((void __iomem *)0xa0702c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int pvr2_init_cable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (cable_type < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PCTRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cable_type = (fb_readw(PDTRA) >> 8) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Now select the output format (either composite or other) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* XXX: Save the previous val first, as this reg is also AICA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (cable_type == CT_COMPOSITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) fb_writel(3 << 8, VOUTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else if (cable_type == CT_RGB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fb_writel(1 << 9, VOUTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fb_writel(0, VOUTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return cable_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int pvr2fb_set_par(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * XXX: It's possible that a user could use a VGA box, change the cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * type in hardware (i.e. switch from VGA<->composite), then change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * modes (i.e. switching to another VT). If that happens we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * automagically change the output format to cope, but currently I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * don't have a VGA box to make sure this works properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cable_type = pvr2_init_cable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (cable_type == CT_VGA && video_output != VO_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) video_output = VO_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) var->vmode &= FB_VMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) par->is_interlaced = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * XXX: Need to be more creative with this (i.e. allow doublecan for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * PAL/NTSC output).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) par->is_doublescan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) par->hsync_total = var->left_margin + var->xres + var->right_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (var->sync & FB_SYNC_BROADCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) vtotal = par->vsync_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (par->is_interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) vtotal /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* XXX: Check for start values here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* XXX: Check hardware for PAL-compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) par->borderstart_h = 116;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) par->borderstart_v = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* NTSC video output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) par->borderstart_h = 126;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) par->borderstart_v = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* VGA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* XXX: What else needs to be checked? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * XXX: We have a little freedom in VGA modes, what ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * should be here (i.e. hsync/vsync totals, etc.)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) par->borderstart_h = 126;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) par->borderstart_v = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Calculate the remainding offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) par->diwstart_h = par->borderstart_h + var->left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) par->diwstart_v = par->borderstart_v + var->upper_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) par->borderstop_h = par->diwstart_h + var->xres +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) var->right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) par->borderstop_v = par->diwstart_v + var->yres +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) var->lower_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!par->is_interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) par->borderstop_v /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (info->var.xres < 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) par->is_lowres = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) info->fix.line_length = line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int vtotal, hsync_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long line_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pr_debug("Invalid pixclock value %d\n", var->pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (var->xres < 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) var->xres = 320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (var->yres < 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) var->yres = 240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (var->xres_virtual < var->xres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) var->xres_virtual = var->xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (var->yres_virtual < var->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) var->yres_virtual = var->yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (var->bits_per_pixel <= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) var->bits_per_pixel = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) else if (var->bits_per_pixel <= 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) var->bits_per_pixel = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) else if (var->bits_per_pixel <= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) var->bits_per_pixel = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) set_color_bitfields(var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (var->vmode & FB_VMODE_YWRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (var->xoffset || var->yoffset >= var->yres_virtual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) var->xoffset = var->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (var->xoffset > var->xres_virtual - var->xres ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) var->yoffset > var->yres_virtual - var->yres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) var->xoffset = var->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) var->xoffset = var->yoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * XXX: Need to be more creative with this (i.e. allow doublecan for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * PAL/NTSC output).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (var->yres < 480 && video_output == VO_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) var->vmode |= FB_VMODE_DOUBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (video_output != VO_VGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) var->sync |= FB_SYNC_BROADCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) var->vmode |= FB_VMODE_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) var->sync &= ~FB_SYNC_BROADCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) var->vmode &= ~FB_VMODE_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) var->vmode |= FB_VMODE_NONINTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) var->right_margin = par->borderstop_h -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (par->diwstart_h + var->xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) var->left_margin = par->diwstart_h - par->borderstart_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) var->hsync_len = par->borderstart_h +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (par->hsync_total - par->borderstop_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) var->upper_margin = par->diwstart_v - par->borderstart_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) var->lower_margin = par->borderstop_v -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (par->diwstart_v + var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) var->vsync_len = par->borderstop_v +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) (par->vsync_total - par->borderstop_v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hsync_total = var->left_margin + var->xres + var->right_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) var->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) vtotal = var->upper_margin + var->yres + var->lower_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) var->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (var->sync & FB_SYNC_BROADCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (var->vmode & FB_VMODE_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) vtotal /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* PAL video output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* XXX: Should be using a range here ... ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (hsync_total != PAL_HTOTAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pr_debug("invalid hsync total for PAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* NTSC video output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (hsync_total != NTSC_HTOTAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pr_debug("invalid hsync total for NTSC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Check memory sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (line_length * var->yres_virtual > info->fix.smem_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void pvr2_update_display(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Update the start address of the display image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fb_writel(par->disp_start, DISP_DIWADDRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fb_writel(par->disp_start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DISP_DIWADDRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * very stable. It's probably due to the fact that a lot of the 2D video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * registers are still undocumented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void pvr2_init_display(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct fb_var_screeninfo *var = &info->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int diw_height, diw_width, diw_modulo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int bytesperpixel = var->bits_per_pixel >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* hsync and vsync totals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* column height, modulo, row width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* since we're "panning" within vram, we need to offset things based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * on the offset from the virtual x start to our real gfx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (video_output != VO_VGA && par->is_interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) diw_modulo += info->fix.line_length / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) DISP_DIWSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* display address, long and short fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fb_writel(par->disp_start, DISP_DIWADDRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fb_writel(par->disp_start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) DISP_DIWADDRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* border horizontal, border vertical, border color */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) fb_writel(0, DISP_BRDRCOLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* display window start position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fb_writel(par->diwstart_h, DISP_DIWHSTRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* misc. settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* clock doubler (for VGA), scan doubler, display enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) fb_writel(((video_output == VO_VGA) << 23) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) (par->is_doublescan << 1) | 1, DISP_DIWMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* bits per pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* video enable, color sync, interlace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * hsync and vsync polarity (currently unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Simulate blanking by making the border cover the entire screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define BLANK_BIT (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void pvr2_do_blank(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct pvr2fb_par *par = currentpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned long diwconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) diwconf = fb_readl(DISP_DIWCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (do_blank > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) is_blanked = do_blank > 0 ? do_blank : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static irqreturn_t __maybe_unused pvr2fb_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct fb_info *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (do_vmode_pan || do_vmode_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pvr2_update_display(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (do_vmode_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pvr2_init_display(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (do_vmode_pan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) do_vmode_pan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (do_vmode_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) do_vmode_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (do_blank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pvr2_do_blank();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) do_blank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #ifdef CONFIG_PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) size_t count, loff_t *ppos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned long dst, start, end, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = pin_user_pages_fast((unsigned long)buf, nr_pages, FOLL_WRITE, pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret < nr_pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * Clamp the unsigned nr_pages to zero so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * error handling works. And leave ret at whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * -errno value was returned from GUP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) nr_pages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) nr_pages = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Use -EINVAL to represent a mildly desperate guess at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * why we got fewer pages (maybe even zero pages) than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dma_configure_channel(shdma, 0x12c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dst = (unsigned long)fb_info->screen_base + *ppos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) start = (unsigned long)page_address(pages[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) end = (unsigned long)page_address(pages[nr_pages]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) len = nr_pages << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Half-assed contig check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (start + len == end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* As we do this in one shot, it's either all or nothing.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if ((*ppos + len) > fb_info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dma_write(shdma, start, 0, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dma_write(pvr2dma, 0, dst, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dma_wait_for_completion(pvr2dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Not contiguous, writeout per-page instead.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dma_write_page(pvr2dma, 0, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dma_wait_for_completion(pvr2dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) *ppos += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unpin_user_pages(pages, nr_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) kfree(pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif /* CONFIG_PVR2_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct fb_ops pvr2fb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .fb_setcolreg = pvr2fb_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .fb_blank = pvr2fb_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .fb_check_var = pvr2fb_check_var,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .fb_set_par = pvr2fb_set_par,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #ifdef CONFIG_PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .fb_write = pvr2fb_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .fb_fillrect = cfb_fillrect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .fb_copyarea = cfb_copyarea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .fb_imageblit = cfb_imageblit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int pvr2_get_param_val(const struct pvr2_params *p, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!strncasecmp(p[i].name, s, strlen(s)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return p[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static char *pvr2_get_param_name(const struct pvr2_params *p, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (p[i].val == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return p[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * pvr2fb_common_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Common init code for the PVR2 chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * This mostly takes care of the common aspects of the fb setup and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * registration. It's expected that the board-specific init code has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * already setup pvr2_fix with something meaningful at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Device info reporting is also done here, as well as picking a sane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * default from the modedb. For board-specific modelines, simply define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * a per-board modedb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * Also worth noting is that the cable and video output types are likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * always going to be VGA for the PCI-based PVR2 boards, but we leave this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * in for flexibility anyways. Who knows, maybe someone has tv-out on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * PCI-based version of these things ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int __maybe_unused pvr2fb_common_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct pvr2fb_par *par = currentpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned long modememused, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fb_info->screen_base = ioremap(pvr2_fix.smem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pvr2_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!fb_info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) par->mmio_base = ioremap(pvr2_fix.mmio_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pvr2_fix.mmio_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (!par->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pvr2_fix.ypanstep = nopan ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pvr2_fix.ywrapstep = nowrap ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fb_info->fbops = &pvr2fb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) fb_info->fix = pvr2_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) fb_info->par = currentpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) fb_info->pseudo_palette = currentpar->palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (video_output == VO_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) defmode = DEFMODE_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!mode_option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mode_option = "640x480@60";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) fb_info->var = pvr2_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) fb_alloc_cmap(&fb_info->cmap, 256, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (register_framebuffer(fb_info) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*Must write PIXDEPTH to register before anything is displayed - so force init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pvr2_init_display(fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) modememused = get_line_length(fb_info->var.xres_virtual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) fb_info->var.bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) modememused *= fb_info->var.yres_virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) rev = fb_readl(par->mmio_base + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) fb_info(fb_info, "%s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) modememused >> 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (unsigned long)(fb_info->fix.smem_len >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) fb_info(fb_info, "Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) fb_info->var.xres, fb_info->var.yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) fb_info->var.bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pvr2_get_param_name(cables, cable_type, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pvr2_get_param_name(outputs, video_output, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #ifdef CONFIG_SH_STORE_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) fb_notice(fb_info, "registering with SQ API\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) fb_info->fix.id, PAGE_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) fb_notice(fb_info, "Mapped video memory to SQ addr 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pvr2fb_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (fb_info->screen_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) iounmap(fb_info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (par->mmio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) iounmap(par->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #ifdef CONFIG_SH_DREAMCAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int __init pvr2fb_dc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!mach_is_dreamcast())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Make a guess at the monitor based on the attached cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (pvr2_init_cable() == CT_VGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) fb_info->monspecs.hfmin = 30000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) fb_info->monspecs.hfmax = 70000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) fb_info->monspecs.vfmin = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) fb_info->monspecs.vfmax = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Not VGA, using a TV (taken from acornfb) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) fb_info->monspecs.hfmin = 15469;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) fb_info->monspecs.hfmax = 15781;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) fb_info->monspecs.vfmin = 49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) fb_info->monspecs.vfmax = 51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * XXX: This needs to pull default video output via BIOS or other means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (video_output < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (cable_type == CT_VGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) video_output = VO_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) video_output = VO_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pvr2_fix.smem_len = 8 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pvr2_fix.mmio_len = 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "pvr2 VBL handler", fb_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #ifdef CONFIG_PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (request_dma(pvr2dma, "pvr2") != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) free_irq(HW_EVENT_VSYNC, fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return pvr2fb_common_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void pvr2fb_dc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (fb_info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) iounmap(fb_info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) fb_info->screen_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (currentpar->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) iounmap(currentpar->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) currentpar->mmio_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) free_irq(HW_EVENT_VSYNC, fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #ifdef CONFIG_PVR2_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) free_dma(pvr2dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #endif /* CONFIG_SH_DREAMCAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int pvr2fb_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) printk(KERN_ERR "pvr2fb: PCI enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = pci_request_regions(pdev, "pvr2fb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * Slightly more exciting than the DC PVR2 .. 16MiB!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) pvr2_fix.smem_start = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) pvr2_fix.smem_len = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) fb_info->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return pvr2fb_common_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static void pvr2fb_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (fb_info->screen_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) iounmap(fb_info->screen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) fb_info->screen_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (currentpar->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) iounmap(currentpar->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) currentpar->mmio_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const struct pci_device_id pvr2fb_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static struct pci_driver pvr2fb_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .name = "pvr2fb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .id_table = pvr2fb_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .probe = pvr2fb_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .remove = pvr2fb_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int __init pvr2fb_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return pci_register_driver(&pvr2fb_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static void pvr2fb_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pci_unregister_driver(&pvr2fb_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * Parse command arguments. Supported arguments are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * inverse Use inverse color maps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * cable:composite|rgb|vga Override the video cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * output:NTSC|PAL|VGA Override the video output format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * <xres>x<yres>[-<bpp>][@<refresh>] or,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * <name>[-<bpp>][@<refresh>] Startup using this video mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static int __init pvr2fb_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) char *this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) char cable_arg[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) char output_arg[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (!options || !*options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) cable_arg[0] = output_arg[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) while ((this_opt = strsep(&options, ","))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!*this_opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (!strcmp(this_opt, "inverse")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) fb_invert_cmaps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) } else if (!strncmp(this_opt, "cable:", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) strcpy(cable_arg, this_opt + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) } else if (!strncmp(this_opt, "output:", 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) strcpy(output_arg, this_opt + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) } else if (!strncmp(this_opt, "nopan", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) nopan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else if (!strncmp(this_opt, "nowrap", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) nowrap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mode_option = this_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (*cable_arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cable_type = pvr2_get_param_val(cables, cable_arg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (*output_arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) video_output = pvr2_get_param_val(outputs, output_arg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static struct pvr2_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int (*init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) void (*exit)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) } board_driver[] __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #ifdef CONFIG_SH_DREAMCAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int __init pvr2fb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int i, ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) char *option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (fb_get_options("pvr2fb", &option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pvr2fb_setup(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!fb_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) currentpar = fb_info->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct pvr2_board *pvr_board = board_driver + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!pvr_board->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = pvr_board->init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pvr_board->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) framebuffer_release(fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static void __exit pvr2fb_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct pvr2_board *pvr_board = board_driver + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (pvr_board->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pvr_board->exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #ifdef CONFIG_SH_STORE_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) sq_unmap(pvr2fb_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) unregister_framebuffer(fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) framebuffer_release(fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) module_init(pvr2fb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) module_exit(pvr2fb_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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