^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP1 Special OptimiSed Screen Interface support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "omapfb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "lcdc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MODULE_NAME "omapfb-sossi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP_SOSSI_BASE 0xfffbac00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOSSI_ID_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SOSSI_INIT1_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOSSI_INIT2_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOSSI_INIT3_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SOSSI_FIFO_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SOSSI_REOTABLE_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SOSSI_TEARING_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SOSSI_INIT1B_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SOSSI_FIFOB_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMA_GSCR 0xfffedc04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_LCD_CCR 0xfffee3c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMA_LCD_CTRL 0xfffee3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMA_LCD_LCH_CTRL 0xfffee3ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CONF_SOSSI_RESET_R (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RD_ACCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WR_ACCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SOSSI_MAX_XMIT_BYTES (512 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long fck_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int bus_pick_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int bus_pick_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int tearsync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int tearsync_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void (*lcdc_callback)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void *lcdc_callback_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int vsync_dma_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* timing for read and write access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 clk_tw0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 clk_tw1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * if last_access is the same as current we don't have to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int last_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct omapfb_device *fbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } sossi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline u32 sossi_read_reg(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return readl(sossi.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline u16 sossi_read_reg16(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return readw(sossi.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline u8 sossi_read_reg8(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return readb(sossi.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline void sossi_write_reg(int reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel(value, sossi.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void sossi_write_reg16(int reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writew(value, sossi.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void sossi_write_reg8(int reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writeb(value, sossi.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void sossi_set_bits(int reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sossi_write_reg(reg, sossi_read_reg(reg) | bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void sossi_clear_bits(int reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HZ_TO_PS(x) (1000000000 / (x / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static u32 ps_to_sossi_ticks(u32 ps, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return (clk_period + ps - 1) / clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int calc_rd_timings(struct extif_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 tw0, tw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int reon, reoff, recyc, actim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int div = t->clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Make sure that after conversion it still holds that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * reoff > reon, recyc >= reoff, actim > reon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) reon = ps_to_sossi_ticks(t->re_on_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* reon will be exactly one sossi tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (reon > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reoff = ps_to_sossi_ticks(t->re_off_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (reoff <= reon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reoff = reon + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tw0 = reoff - reon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (tw0 > 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (recyc <= reoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) recyc = reoff + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tw1 = recyc - tw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* values less then 3 result in the SOSSI block resetting itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (tw1 < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tw1 = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (tw1 > 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) actim = ps_to_sossi_ticks(t->access_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (actim < reoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) actim++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * access time (data hold time) will be exactly one sossi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (actim - reoff > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) t->tim[0] = tw0 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) t->tim[1] = tw1 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int calc_wr_timings(struct extif_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 tw0, tw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int weon, weoff, wecyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int div = t->clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Make sure that after conversion it still holds that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * weoff > weon, wecyc >= weoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) weon = ps_to_sossi_ticks(t->we_on_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* weon will be exactly one sossi tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (weon > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) weoff = ps_to_sossi_ticks(t->we_off_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (weoff <= weon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) weoff = weon + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tw0 = weoff - weon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (tw0 > 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (wecyc <= weoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) wecyc = weoff + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tw1 = wecyc - tw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* values less then 3 result in the SOSSI block resetting itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (tw1 < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tw1 = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (tw1 > 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) t->tim[2] = tw0 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) t->tim[3] = tw1 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void _set_timing(int div, int tw0, int tw1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tw0 + 1, tw1 + 1, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_set_rate(sossi.fck, sossi.fck_hz / div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) l = sossi_read_reg(SOSSI_INIT1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) l &= ~((0x0f << 20) | (0x3f << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) l |= (tw0 << 20) | (tw1 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sossi_write_reg(SOSSI_INIT1_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) l = sossi_read_reg(SOSSI_INIT3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) l &= ~0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sossi_write_reg(SOSSI_INIT3_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void _set_tearsync_mode(int mode, unsigned line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) l = sossi_read_reg(SOSSI_TEARING_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) l &= ~(((1 << 11) - 1) << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) l |= line << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) l &= ~(0x3 << 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) l |= mode << 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sossi_write_reg(SOSSI_TEARING_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline void set_timing(int access)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (access != sossi.last_access) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) sossi.last_access = access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) _set_timing(sossi.clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sossi.clk_tw0[access], sossi.clk_tw1[access]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void sossi_start_transfer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* WE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* CS active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void sossi_stop_transfer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* WE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* CS active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void wait_end_of_write(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Before reading we must check if some writings are going on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void send_data(const void *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) while (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) data += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void set_cycles(unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) BUG_ON((nr_cycles - 1) & ~0x3ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int sossi_convert_timings(struct extif_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int div = t->clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) t->converted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (div <= 0 || div > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if ((r = calc_rd_timings(t)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if ((r = calc_wr_timings(t)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) t->tim[4] = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) t->converted = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void sossi_set_timings(const struct extif_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) BUG_ON(!t->converted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sossi.clk_tw0[RD_ACCESS] = t->tim[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) sossi.clk_tw1[RD_ACCESS] = t->tim[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sossi.clk_tw0[WR_ACCESS] = t->tim[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sossi.clk_tw1[WR_ACCESS] = t->tim[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sossi.clk_div = t->tim[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *clk_period = HZ_TO_PS(sossi.fck_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *max_clk_div = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void sossi_set_bits_per_cycle(int bpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int bus_pick_count, bus_pick_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * We set explicitly the the bus_pick_count as well, although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * with remapping/reordering disabled it will be calculated by HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * as (32 / bus_pick_width).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) switch (bpc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bus_pick_count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bus_pick_width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bus_pick_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) bus_pick_width = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sossi.bus_pick_width = bus_pick_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sossi.bus_pick_count = bus_pick_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int sossi_setup_tearsync(unsigned pin_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned hs_pulse_time, unsigned vs_pulse_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int hs_pol_inv, int vs_pol_inv, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int hs, vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (pin_cnt != 1 || div < 1 || div > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hs = ps_to_sossi_ticks(hs_pulse_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) vs = ps_to_sossi_ticks(vs_pulse_time, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (vs < 8 || vs <= hs || vs >= (1 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) vs /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) vs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (hs > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hs = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (hs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_dbg(sossi.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) hs, vs, hs_pol_inv, vs_pol_inv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) l = sossi_read_reg(SOSSI_TEARING_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) l &= ~((1 << 15) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) l |= vs << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) l |= hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (hs_pol_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) l |= 1 << 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) l &= ~(1 << 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (vs_pol_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) l |= 1 << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) l &= ~(1 << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sossi_write_reg(SOSSI_TEARING_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int sossi_enable_tearsync(int enable, unsigned line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (line >= 1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mode = 2; /* HS or VS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mode = 3; /* VS only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sossi.tearsync_line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sossi.tearsync_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void sossi_write_command(const void *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) set_timing(WR_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* CMD#/DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) set_cycles(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sossi_start_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) send_data(data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sossi_stop_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wait_end_of_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void sossi_write_data(const void *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) set_timing(WR_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* CMD#/DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) set_cycles(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sossi_start_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) send_data(data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sossi_stop_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) wait_end_of_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void sossi_transfer_area(int width, int height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void (callback)(void *data), void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) BUG_ON(callback == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sossi.lcdc_callback = callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) sossi.lcdc_callback_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) set_timing(WR_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) _set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* CMD#/DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) set_cycles(width * height * sossi.bus_pick_width / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sossi_start_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (sossi.tearsync_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Wait for the sync signal and start the transfer only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * then. We can't seem to be able to use HW sync DMA for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * this since LCD DMA shows huge latencies, as if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * would ignore some of the DMA requests from SoSSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_lock_irqsave(&sossi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sossi.vsync_dma_pending++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_unlock_irqrestore(&sossi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Just start the transfer right away. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) omap_enable_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void sossi_dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) omap_stop_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sossi_stop_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sossi.lcdc_callback(sossi.lcdc_callback_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void sossi_read_data(void *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) set_timing(RD_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* CMD#/DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) set_cycles(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sossi_start_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) while (len >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sossi_stop_transfer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static irqreturn_t sossi_match_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) spin_lock_irqsave(&sossi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (sossi.vsync_dma_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sossi.vsync_dma_pending--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) omap_enable_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) spin_unlock_irqrestore(&sossi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int sossi_init(struct omapfb_device *fbdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 l, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct clk *fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct clk *dpll1out_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!sossi.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(fbdev->dev, "can't ioremap SoSSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sossi.fbdev = fbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_lock_init(&sossi.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (IS_ERR(dpll1out_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_err(fbdev->dev, "can't get DPLL1OUT clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return PTR_ERR(dpll1out_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * We need the parent clock rate, which we might divide further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * depending on the timing requirements of the controller. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * _set_timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) sossi.fck_hz = clk_get_rate(dpll1out_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) clk_put(dpll1out_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) fck = clk_get(fbdev->dev, "ck_sossi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (IS_ERR(fck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(fbdev->dev, "can't get SoSSI functional clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return PTR_ERR(fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) sossi.fck = fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Reset and enable the SoSSI module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) l = omap_readl(MOD_CONF_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) l |= CONF_SOSSI_RESET_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) omap_writel(l, MOD_CONF_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) l &= ~CONF_SOSSI_RESET_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) omap_writel(l, MOD_CONF_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) clk_enable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) l = omap_readl(ARM_IDLECT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) l &= ~(1 << 8); /* DMACK_REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) omap_writel(l, ARM_IDLECT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) l = sossi_read_reg(SOSSI_INIT2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Enable and reset the SoSSI block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) l |= (1 << 0) | (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sossi_write_reg(SOSSI_INIT2_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Take SoSSI out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) l &= ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) sossi_write_reg(SOSSI_INIT2_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sossi_write_reg(SOSSI_ID_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) l = sossi_read_reg(SOSSI_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) k = sossi_read_reg(SOSSI_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (l != 0x55555555 || k != 0xaaaaaaaa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "invalid SoSSI sync pattern: %08x, %08x\n", l, k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) r = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(fbdev->dev, "can't get LCDC IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) r = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) l = sossi_read_reg(SOSSI_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) l >> 16, l & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) l = sossi_read_reg(SOSSI_INIT1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) l |= (1 << 19); /* DMA_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) l &= ~(1 << 31); /* REORDERING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sossi_write_reg(SOSSI_INIT1_REG, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) IRQ_TYPE_EDGE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "sossi_match", sossi.fbdev->dev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) clk_disable(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) clk_put(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void sossi_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) omap_lcdc_free_dma_callback();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) clk_put(sossi.fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) iounmap(sossi.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct lcd_ctrl_extif omap1_ext_if = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .init = sossi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .cleanup = sossi_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .get_clk_info = sossi_get_clk_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .convert_timings = sossi_convert_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .set_timings = sossi_set_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .set_bits_per_cycle = sossi_set_bits_per_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .setup_tearsync = sossi_setup_tearsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .enable_tearsync = sossi_enable_tearsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .write_command = sossi_write_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .read_data = sossi_read_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .write_data = sossi_write_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .transfer_area = sossi_transfer_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .max_transmit_size = SOSSI_MAX_XMIT_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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