^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP1 internal LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Imre Deak <imre.deak@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <mach/lcdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "omapfb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "lcdc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MODULE_NAME "lcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX_PALETTE_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum lcdc_load_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) OMAP_LCDC_LOAD_PALETTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) OMAP_LCDC_LOAD_FRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) OMAP_LCDC_LOAD_PALETTE_AND_FRAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct omap_lcd_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum omapfb_update_mode update_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ext_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long frame_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int screen_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum omapfb_color_format color_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void *palette_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dma_addr_t palette_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int palette_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int palette_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct completion last_frame_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct completion palette_load_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct clk *lcd_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct omapfb_device *fbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void (*dma_callback)(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void *dma_callback_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dma_addr_t vram_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void *vram_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long vram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } lcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void enable_irqs(int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) lcdc.irq_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void disable_irqs(int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) lcdc.irq_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void set_load_mode(enum lcdc_load_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) l = omap_readl(OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) l &= ~(3 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case OMAP_LCDC_LOAD_PALETTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) l |= 1 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case OMAP_LCDC_LOAD_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) l |= 2 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) omap_writel(l, OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void enable_controller(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) l = omap_readl(OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) l |= OMAP_LCDC_CTRL_LCD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) l &= ~OMAP_LCDC_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) omap_writel(l, OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void disable_controller_async(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) l = omap_readl(OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Preserve the DONE mask, since we still want to get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * final DONE irq. It will be disabled in the IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mask &= ~OMAP_LCDC_IRQ_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) l &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) omap_writel(l, OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void disable_controller(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) init_completion(&lcdc.last_frame_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) disable_controller_async();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msecs_to_jiffies(500)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void reset_controller(u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static unsigned long reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static unsigned long last_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) disable_controller_async();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reset_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(lcdc.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "resetting (status %#010x,reset count %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) status, reset_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) last_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (reset_count < 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reset_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(lcdc.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "too many reset attempts, giving up.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Configure the LCD DMA according to the current mode specified by parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * in lcdc.fbdev and fbdev->var.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void setup_lcd_dma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const int dma_elem_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) OMAP_DMA_DATA_TYPE_S8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) OMAP_DMA_DATA_TYPE_S16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) OMAP_DMA_DATA_TYPE_S32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int esize, xelem, yelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) src = lcdc.vram_phys + lcdc.frame_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) switch (var->rotate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (plane->info.mirror || (src & 3) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (lcdc.xres & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) esize = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) esize = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) xelem = lcdc.xres * lcdc.bpp / 8 / esize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) yelem = lcdc.yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) esize = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) xelem = lcdc.yres * lcdc.bpp / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) yelem = lcdc.xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_dbg(lcdc.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) src, esize, xelem, yelem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int bpp = lcdc.bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * YUV support is only for external mode when we have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * YUV window embedded in a 16bpp frame buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bpp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Set virtual xres elem size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) omap_set_lcd_dma_b1_vxres(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) lcdc.screen_width * bpp / 8 / esize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Setup transformations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) omap_set_lcd_dma_b1_rotation(var->rotate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) omap_set_lcd_dma_b1_mirror(plane->info.mirror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) omap_setup_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) status = omap_readl(OMAP_LCDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reset_controller(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (status & OMAP_LCDC_STAT_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Disable IRQ_DONE. The status bit will be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * only when the controller is reenabled and we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * want to get more interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) l = omap_readl(OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) l &= ~OMAP_LCDC_IRQ_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) omap_writel(l, OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) complete(&lcdc.last_frame_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) disable_controller_async();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) complete(&lcdc.palette_load_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Clear these interrupt status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Sync_lost, FUF bits were cleared by disabling the LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * LOADED_PALETTE can be cleared this way only in palette only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * load mode. In other load modes it's cleared by disabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) status &= ~(OMAP_LCDC_STAT_VSYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) OMAP_LCDC_STAT_LOADED_PALETTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) OMAP_LCDC_STAT_ABC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) OMAP_LCDC_STAT_LINE_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) omap_writel(status, OMAP_LCDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Change to a new video mode. We defer this to a later time to avoid any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * flicker and not to mess up the current LCD DMA context. For this we disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * the LCD controller, which will generate a DONE irq after the last frame has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * been transferred. Then it'll be safe to reconfigure both the LCD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * as well as the LCD DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int omap_lcdc_setup_plane(int plane, int channel_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long offset, int screen_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int pos_x, int pos_y, int width, int height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int color_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct lcd_panel *panel = lcdc.fbdev->panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int rot_x, rot_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (var->rotate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rot_x = panel->x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rot_y = panel->y_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rot_x = panel->y_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rot_y = panel->x_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) width > rot_x || height > rot_y) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #ifdef VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_dbg(lcdc.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "invalid plane params plane %d pos_x %d pos_y %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "w %d h %d\n", plane, pos_x, pos_y, width, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) lcdc.frame_offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) lcdc.xres = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) lcdc.yres = height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) lcdc.screen_width = screen_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) lcdc.color_mode = color_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) switch (color_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case OMAPFB_COLOR_CLUT_8BPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) lcdc.bpp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) lcdc.palette_code = 0x3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) lcdc.palette_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case OMAPFB_COLOR_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) lcdc.bpp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) lcdc.palette_code = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) lcdc.palette_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case OMAPFB_COLOR_RGB444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) lcdc.bpp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) lcdc.palette_code = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) lcdc.palette_size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case OMAPFB_COLOR_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (lcdc.ext_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) lcdc.bpp = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case OMAPFB_COLOR_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (lcdc.ext_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) lcdc.bpp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* FIXME: other BPPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * bpp1: code 0, size 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * bpp2: code 0x1000 size 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * bpp4: code 0x2000 size 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * bpp12: code 0x4000 size 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (lcdc.ext_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) setup_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) disable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) omap_stop_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) setup_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) enable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int omap_lcdc_enable_plane(int plane, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_dbg(lcdc.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "plane %d enable %d update_mode %d ext_mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) plane, enable, lcdc.update_mode, lcdc.ext_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (plane != OMAPFB_PLANE_GFX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Configure the LCD DMA for a palette load operation and do the palette
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * downloading synchronously. We don't use the frame+palette load mode of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * the controller, since the palette can always be downloaded separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void load_palette(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u16 *palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) palette = (u16 *)lcdc.palette_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *(u16 *)palette &= 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *(u16 *)palette |= lcdc.palette_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) omap_set_lcd_dma_b1(lcdc.palette_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) omap_set_lcd_dma_single_transfer(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) omap_setup_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) init_completion(&lcdc.palette_load_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) set_load_mode(OMAP_LCDC_LOAD_PALETTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msecs_to_jiffies(500)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* The controller gets disabled in the irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) omap_stop_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Used only in internal controller mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u16 transp, int update_hw_pal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u16 *palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) palette = (u16 *)lcdc.palette_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) palette[regno] &= ~0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (blue >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (update_hw_pal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) disable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) omap_stop_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) load_palette();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) setup_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) set_load_mode(OMAP_LCDC_LOAD_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) enable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void calc_ck_div(int is_tft, int pck, int *pck_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long lck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pck = max(1, pck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) lck = clk_get_rate(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *pck_div = (lck + pck - 1) / pck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (is_tft)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *pck_div = max(2, *pck_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) *pck_div = max(3, *pck_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (*pck_div > 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* FIXME: try to adjust logic clock divider as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *pck_div = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pck / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static inline void setup_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct lcd_panel *panel = lcdc.fbdev->panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long lck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int pcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) l = omap_readl(OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) l &= ~OMAP_LCDC_CTRL_LCD_TFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #ifdef CONFIG_MACH_OMAP_PALMTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* FIXME:if (machine_is_omap_palmte()) { */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* PalmTE uses alternate TFT setting in 8BPP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) omap_writel(l, OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) l = omap_readl(OMAP_LCDC_TIMING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) l &= ~(((1 << 6) - 1) << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) omap_writel(l, OMAP_LCDC_TIMING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) l = panel->x_res - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) l |= (panel->hsw - 1) << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) l |= (panel->hfp - 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) l |= (panel->hbp - 1) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) omap_writel(l, OMAP_LCDC_TIMING0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) l = panel->y_res - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) l |= (panel->vsw - 1) << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) l |= panel->vfp << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) l |= panel->vbp << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) omap_writel(l, OMAP_LCDC_TIMING1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) l = omap_readl(OMAP_LCDC_TIMING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) l &= ~0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) lck = clk_get_rate(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!panel->pcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_warn(lcdc.fbdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "Pixel clock divider value is obsolete.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "Try to set pixel_clock to %lu and pcd to 0 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) lck / panel->pcd / 1000, panel->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pcd = panel->pcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) l |= pcd & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) l |= panel->acb << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) omap_writel(l, OMAP_LCDC_TIMING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* update panel info with the exact clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) panel->pixel_clock = lck / pcd / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Configure the LCD controller, download the color palette and start a looped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * DMA transfer of the frame image data. Called only in internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * controller mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (mode != lcdc.update_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case OMAPFB_AUTO_UPDATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) setup_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) load_palette();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Setup and start LCD DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) setup_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) set_load_mode(OMAP_LCDC_LOAD_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) enable_irqs(OMAP_LCDC_IRQ_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* This will start the actual DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) enable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) lcdc.update_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case OMAPFB_UPDATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) disable_controller();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) omap_stop_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) lcdc.update_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return lcdc.update_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* PM code called only in internal controller mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void omap_lcdc_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static void omap_lcdc_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) BUG_ON(callback == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (lcdc.dma_callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) lcdc.dma_callback = callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) lcdc.dma_callback_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void omap_lcdc_free_dma_callback(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) lcdc.dma_callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void lcdc_dma_handler(u16 status, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (lcdc.dma_callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) lcdc.dma_callback(lcdc.dma_callback_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int alloc_palette_ram(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) lcdc.palette_virt = dma_alloc_wc(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &lcdc.palette_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (lcdc.palette_virt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static void free_palette_ram(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dma_free_wc(lcdc.fbdev->dev, MAX_PALETTE_SIZE, lcdc.palette_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) lcdc.palette_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int alloc_fbmem(struct omapfb_mem_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct lcd_panel *panel = lcdc.fbdev->panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) bpp = panel->bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (bpp == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bpp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (region->size > frame_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) frame_size = region->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) lcdc.vram_size = frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) lcdc.vram_virt = dma_alloc_wc(lcdc.fbdev->dev, lcdc.vram_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) &lcdc.vram_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (lcdc.vram_virt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) region->size = frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) region->paddr = lcdc.vram_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) region->vaddr = lcdc.vram_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) region->alloc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) memset(lcdc.vram_virt, 0, lcdc.vram_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void free_fbmem(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dma_free_wc(lcdc.fbdev->dev, lcdc.vram_size, lcdc.vram_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) lcdc.vram_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int setup_fbmem(struct omapfb_mem_desc *req_md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!req_md->region_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (req_md->region_cnt > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) req_md->region_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return alloc_fbmem(&req_md->region[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct omapfb_mem_desc *req_vram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct clk *tc_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) lcdc.irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) lcdc.fbdev = fbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) lcdc.ext_mode = ext_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) omap_writel(l, OMAP_LCDC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * According to errata some platforms have a clock rate limitiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (IS_ERR(lcdc.lcd_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(fbdev->dev, "unable to access LCD clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) r = PTR_ERR(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tc_ck = clk_get(fbdev->dev, "tc_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (IS_ERR(tc_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(fbdev->dev, "unable to access TC clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) r = PTR_ERR(tc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rate = clk_get_rate(tc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) clk_put(tc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (machine_is_ams_delta())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rate /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (machine_is_omap_h3())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) rate /= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) r = clk_set_rate(lcdc.lcd_ck, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_err(fbdev->dev, "failed to adjust LCD rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk_enable(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(fbdev->dev, "unable to get IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(fbdev->dev, "unable to get LCD DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) omap_set_lcd_dma_single_transfer(ext_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) omap_set_lcd_dma_ext_controller(ext_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!ext_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if ((r = alloc_palette_ram()) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto fail4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if ((r = setup_fbmem(req_vram)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) goto fail5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pr_info("omapfb: LCDC initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) fail5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!ext_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) free_palette_ram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) fail4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) omap_free_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) fail3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) clk_disable(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clk_put(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void omap_lcdc_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!lcdc.ext_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) free_palette_ram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) free_fbmem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) omap_free_lcd_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) clk_disable(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) clk_put(lcdc.lcd_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) const struct lcd_ctrl omap1_int_ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .name = "internal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .init = omap_lcdc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .cleanup = omap_lcdc_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .get_caps = omap_lcdc_get_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .set_update_mode = omap_lcdc_set_update_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .get_update_mode = omap_lcdc_get_update_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .update_window = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .suspend = omap_lcdc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .resume = omap_lcdc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .setup_plane = omap_lcdc_setup_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .enable_plane = omap_lcdc_enable_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .setcolreg = omap_lcdc_setcolreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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