^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __MB862XX_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __MB862XX_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) struct mb862xx_l1_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) unsigned short sx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) unsigned short sy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) unsigned short sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) unsigned short sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) unsigned short dx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) unsigned short dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) unsigned short dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) unsigned short dh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) int mirror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MB862XX_BASE 'M'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_DEVICE_ID_FUJITSU_CARMINE 0x202b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GC_MMR_CORALP_EVB_VAL 0x11d7fa13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum gdctype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) BT_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) BT_LIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) BT_MINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) BT_CORAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BT_CORALP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) BT_CARMINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct mb862xx_gc_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct fb_videomode def_mode; /* mode of connected display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int def_bpp; /* default depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long max_vram; /* connected SDRAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long ccf; /* gdc clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long mmr; /* memory mode for SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mb862xxfb_par {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct fb_info *info; /* fb info head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct resource *res; /* framebuffer/mmio resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) resource_size_t fb_base_phys; /* fb base, 36-bit PPC440EPx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) resource_size_t mmio_base_phys; /* io base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *fb_base; /* remapped framebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *mmio_base; /* remapped registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) size_t mapped_vram; /* length of remapped vram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) size_t mmio_len; /* length of register region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long cap_buf; /* capture buffers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) size_t cap_len; /* length of capture buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *host; /* relocatable reg. bases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __iomem *disp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *cap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *draw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *geo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *dram_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __iomem *wrback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int type; /* GDC type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int refclk; /* disp. reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int pre_init; /* don't init display if 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct i2c_adapter *adap; /* GDC I2C bus adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int i2c_rs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mb862xx_l1_cfg l1_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int l1_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 pseudo_palette[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern void mb862xxfb_init_accel(struct fb_info *info, struct fb_ops *fbops, int xres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifdef CONFIG_FB_MB862XX_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #error "Select Lime GDC or CoralP/Carmine support, but not both together"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #if defined(CONFIG_FB_MB862XX_LIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define gdc_read __raw_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define gdc_write __raw_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define gdc_read readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define gdc_write writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define inreg(type, off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) gdc_read((par->type + (off)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define outreg(type, off, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gdc_write((val), (par->type + (off)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define pack(a, b) (((a) << 16) | (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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