^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/video/kyro/STG4000Reg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2002 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _STG4000REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _STG4000REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DWFILL unsigned long :32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WFILL unsigned short :16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Macros that access memory mapped card registers in PCI space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Add an appropriate section for your OS or processor architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #if defined(__KERNEL__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STG_WRITE_REG(reg,data) (writel(data,&pSTGReg->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STG_READ_REG(reg) (readl(&pSTGReg->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STG_WRITE_REG(reg,data) (pSTGReg->reg = data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STG_READ_REG(reg) (pSTGReg->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SET_BIT(n) (1<<(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLEAR_BIT(n) (tmp &= ~(1<<n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLEAR_BITS_FRM_TO(frm, to) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) for(i = frm; i<= to; i++) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) tmp &= ~(1<<i); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLEAR_BIT_2(n) (usTemp &= ~(1<<n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLEAR_BITS_FRM_TO_2(frm, to) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for(i = frm; i<= to; i++) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) usTemp &= ~(1<<i); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* LUT select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) typedef enum _LUT_USES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } LUT_USES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Primary surface pixel format select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) typedef enum _PIXEL_FORMAT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } PIXEL_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Overlay blending mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) typedef enum _BLEND_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CK_PIXEL_ALPHA, CK_GLOBAL_ALPHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } OVRL_BLEND_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Overlay Pixel format select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) typedef enum _OVRL_PIX_FORMAT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) UYVY, VYUY, YUYV, YVYU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } OVRL_PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Register Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* 0h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) volatile u32 Thread0Enable; /* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) volatile u32 Thread1Enable; /* 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) volatile u32 Thread0Recover; /* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) volatile u32 Thread1Recover; /* 0x000C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) volatile u32 Thread0Step; /* 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) volatile u32 Thread1Step; /* 0x0014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) volatile u32 VideoInStatus; /* 0x0018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) volatile u32 Core2InSignStart; /* 0x001C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) volatile u32 Core1ResetVector; /* 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) volatile u32 Core1ROMOffset; /* 0x0024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) volatile u32 Core1ArbiterPriority; /* 0x0028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) volatile u32 VideoInControl; /* 0x002C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) volatile u32 VideoInReg0CtrlA; /* 0x0030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) volatile u32 VideoInReg0CtrlB; /* 0x0034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) volatile u32 VideoInReg1CtrlA; /* 0x0038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) volatile u32 VideoInReg1CtrlB; /* 0x003C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) volatile u32 Thread0Kicker; /* 0x0040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) volatile u32 Core2InputSign; /* 0x0044 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) volatile u32 Thread0ProgCtr; /* 0x0048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) volatile u32 Thread1ProgCtr; /* 0x004C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) volatile u32 Thread1Kicker; /* 0x0050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) volatile u32 GPRegister1; /* 0x0054 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) volatile u32 GPRegister2; /* 0x0058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) volatile u32 GPRegister3; /* 0x005C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) volatile u32 GPRegister4; /* 0x0060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) volatile u32 SerialIntA; /* 0x0064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) volatile u32 Fill0[6]; /* GAP 0x0068 - 0x007C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) volatile u32 SoftwareReset; /* 0x0080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) volatile u32 SerialIntB; /* 0x0084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) volatile u32 Fill1[37]; /* GAP 0x0088 - 0x011C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) volatile u32 ROMELQV; /* 0x011C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) volatile u32 WLWH; /* 0x0120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) volatile u32 ROMELWL; /* 0x0124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) volatile u32 dwFill_1; /* GAP 0x0128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) volatile u32 IntStatus; /* 0x012C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) volatile u32 IntMask; /* 0x0130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) volatile u32 IntClear; /* 0x0134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) volatile u32 Fill2[6]; /* GAP 0x0138 - 0x014C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) volatile u32 ROMGPIOA; /* 0x0150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) volatile u32 ROMGPIOB; /* 0x0154 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) volatile u32 ROMGPIOC; /* 0x0158 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) volatile u32 ROMGPIOD; /* 0x015C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) volatile u32 Fill3[2]; /* GAP 0x0160 - 0x0168 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) volatile u32 AGPIntID; /* 0x0168 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) volatile u32 AGPIntClassCode; /* 0x016C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) volatile u32 AGPIntBIST; /* 0x0170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) volatile u32 AGPIntSSID; /* 0x0174 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) volatile u32 AGPIntPMCSR; /* 0x0178 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) volatile u32 VGAFrameBufBase; /* 0x017C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) volatile u32 VGANotify; /* 0x0180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) volatile u32 DACPLLMode; /* 0x0184 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) volatile u32 Core1VideoClockDiv; /* 0x0188 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) volatile u32 AGPIntStat; /* 0x018C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) volatile u32 Fill4[0x0400/4 - 0x0190/4]; //GAP 0x0190 - 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) volatile u32 Fill5[0x05FC/4 - 0x0400/4]; //GAP 0x0400 - 0x05FC Fog Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) volatile u32 Fill6[0x0604/4 - 0x0600/4]; //GAP 0x0600 - 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) volatile u32 Fill7[0x0680/4 - 0x0608/4]; //GAP 0x0608 - 0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) volatile u32 Fill8[0x07FC/4 - 0x0684/4]; //GAP 0x0684 - 0x07FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) volatile u32 Fill4[412]; /* 0x0190 - 0x07FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) volatile u32 TACtrlStreamBase; /* 0x0800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) volatile u32 TAObjDataBase; /* 0x0804 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) volatile u32 TAPtrDataBase; /* 0x0808 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) volatile u32 TARegionDataBase; /* 0x080C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) volatile u32 TATailPtrBase; /* 0x0810 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) volatile u32 TAPtrRegionSize; /* 0x0814 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) volatile u32 TAConfiguration; /* 0x0818 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) volatile u32 TAObjDataStartAddr; /* 0x081C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) volatile u32 TAObjDataEndAddr; /* 0x0820 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) volatile u32 TAXScreenClip; /* 0x0824 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) volatile u32 TAYScreenClip; /* 0x0828 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) volatile u32 TARHWClamp; /* 0x082C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) volatile u32 TARHWCompare; /* 0x0830 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) volatile u32 TAStart; /* 0x0834 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) volatile u32 TAObjReStart; /* 0x0838 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) volatile u32 TAPtrReStart; /* 0x083C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) volatile u32 TAStatus1; /* 0x0840 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) volatile u32 TAStatus2; /* 0x0844 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) volatile u32 TAIntStatus; /* 0x0848 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) volatile u32 TAIntMask; /* 0x084C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) volatile u32 Fill5[235]; /* GAP 0x0850 - 0x0BF8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) volatile u32 TextureAddrThresh; /* 0x0BFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) volatile u32 Core1Translation; /* 0x0C00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) volatile u32 TextureAddrReMap; /* 0x0C04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) volatile u32 RenderOutAGPRemap; /* 0x0C08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) volatile u32 _3DRegionReadTrans; /* 0x0C0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) volatile u32 _3DPtrReadTrans; /* 0x0C10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) volatile u32 _3DParamReadTrans; /* 0x0C14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) volatile u32 _3DRegionReadThresh; /* 0x0C18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) volatile u32 _3DPtrReadThresh; /* 0x0C1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) volatile u32 _3DParamReadThresh; /* 0x0C20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) volatile u32 _3DRegionReadAGPRemap; /* 0x0C24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) volatile u32 _3DPtrReadAGPRemap; /* 0x0C28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) volatile u32 _3DParamReadAGPRemap; /* 0x0C2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) volatile u32 ZBufferAGPRemap; /* 0x0C30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) volatile u32 TAIndexAGPRemap; /* 0x0C34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) volatile u32 TAVertexAGPRemap; /* 0x0C38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) volatile u32 TAUVAddrTrans; /* 0x0C3C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) volatile u32 TATailPtrCacheTrans; /* 0x0C40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) volatile u32 TAParamWriteTrans; /* 0x0C44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) volatile u32 TAPtrWriteTrans; /* 0x0C48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) volatile u32 TAParamWriteThresh; /* 0x0C4C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) volatile u32 TAPtrWriteThresh; /* 0x0C50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) volatile u32 TATailPtrCacheAGPRe; /* 0x0C54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) volatile u32 TAParamWriteAGPRe; /* 0x0C58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) volatile u32 TAPtrWriteAGPRe; /* 0x0C5C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) volatile u32 SDRAMArbiterConf; /* 0x0C60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) volatile u32 SDRAMConf0; /* 0x0C64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) volatile u32 SDRAMConf1; /* 0x0C68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) volatile u32 SDRAMConf2; /* 0x0C6C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) volatile u32 SDRAMRefresh; /* 0x0C70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) volatile u32 SDRAMPowerStat; /* 0x0C74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) volatile u32 Fill6[2]; /* GAP 0x0C78 - 0x0C7C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) volatile u32 RAMBistData; /* 0x0C80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) volatile u32 RAMBistCtrl; /* 0x0C84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) volatile u32 FIFOBistKey; /* 0x0C88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) volatile u32 RAMBistResult; /* 0x0C8C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) volatile u32 FIFOBistResult; /* 0x0C90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) volatile u32 Fill11[0x0CBC/4 - 0x0C94/4]; //GAP 0x0C94 - 0x0CBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) volatile u32 Fill12[0x0CD0/4 - 0x0CC0/4]; //GAP 0x0CC0 - 0x0CD0 3DRegisters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) volatile u32 Fill7[16]; /* 0x0c94 - 0x0cd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) volatile u32 SDRAMAddrSign; /* 0x0CD4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) volatile u32 SDRAMDataSign; /* 0x0CD8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) volatile u32 SDRAMSignConf; /* 0x0CDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* DWFILL; //GAP 0x0CE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) volatile u32 dwFill_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) volatile u32 ISPSignature; /* 0x0CE4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) volatile u32 Fill8[454]; /*GAP 0x0CE8 - 0x13FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) volatile u32 DACPrimAddress; /* 0x1400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) volatile u32 DACPrimSize; /* 0x1404 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) volatile u32 DACCursorAddr; /* 0x1408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) volatile u32 DACCursorCtrl; /* 0x140C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) volatile u32 DACOverlayAddr; /* 0x1410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) volatile u32 DACOverlayUAddr; /* 0x1414 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) volatile u32 DACOverlayVAddr; /* 0x1418 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) volatile u32 DACOverlaySize; /* 0x141C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) volatile u32 DACOverlayVtDec; /* 0x1420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) volatile u32 Fill9[9]; /* GAP 0x1424 - 0x1444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) volatile u32 DACVerticalScal; /* 0x1448 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) volatile u32 DACPixelFormat; /* 0x144C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) volatile u32 DACHorizontalScal; /* 0x1450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) volatile u32 DACVidWinStart; /* 0x1454 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) volatile u32 DACVidWinEnd; /* 0x1458 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) volatile u32 DACBlendCtrl; /* 0x145C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) volatile u32 DACHorTim1; /* 0x1460 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) volatile u32 DACHorTim2; /* 0x1464 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) volatile u32 DACHorTim3; /* 0x1468 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) volatile u32 DACVerTim1; /* 0x146C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) volatile u32 DACVerTim2; /* 0x1470 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) volatile u32 DACVerTim3; /* 0x1474 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) volatile u32 DACBorderColor; /* 0x1478 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) volatile u32 DACSyncCtrl; /* 0x147C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) volatile u32 DACStreamCtrl; /* 0x1480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) volatile u32 DACLUTAddress; /* 0x1484 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) volatile u32 DACLUTData; /* 0x1488 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) volatile u32 DACBurstCtrl; /* 0x148C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) volatile u32 DACCrcTrigger; /* 0x1490 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) volatile u32 DACCrcDone; /* 0x1494 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) volatile u32 DACCrcResult1; /* 0x1498 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) volatile u32 DACCrcResult2; /* 0x149C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) volatile u32 DACLinecount; /* 0x14A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) volatile u32 Fill10[151]; /*GAP 0x14A4 - 0x16FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) volatile u32 DigVidPortCtrl; /* 0x1700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) volatile u32 DigVidPortStat; /* 0x1704 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) volatile u32 Fill11[0x1FFC/4 - 0x1708/4]; //GAP 0x1708 - 0x1FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) volatile u32 Fill17[0x3000/4 - 0x2FFC/4]; //GAP 0x2000 - 0x2FFC ALUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) volatile u32 Fill11[1598];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* DWFILL; //GAP 0x3000 ALUT 256MB offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) volatile u32 Fill_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } STG4000REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif /* _STG4000REG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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