Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *  linux/drivers/video/kyro/STG4000Interface.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *  Copyright (C) 2002 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * License.  See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _STG4000INTERFACE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _STG4000INTERFACE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/kyro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * Ramdac Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) extern int InitialiseRamdac(volatile STG4000REG __iomem *pSTGReg, u32 displayDepth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			    u32 displayWidth, u32 displayHeight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			    s32 HSyncPolarity, s32 VSyncPolarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			    u32 *pixelClock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern void DisableRamdacOutput(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern void EnableRamdacOutput(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * Timing generator setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern void DisableVGA(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) extern void StopVTG(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern void StartVTG(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern void SetupVTG(volatile STG4000REG __iomem *pSTGReg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		     const struct kyrofb_info * pTiming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern u32 ProgramClock(u32 refClock, u32 coreClock, u32 *FOut, u32 *ROut, u32 *POut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * Overlay setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern void ResetOverlayRegisters(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) extern int CreateOverlaySurface(volatile STG4000REG __iomem *pSTGReg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				u32 ulWidth, u32 ulHeight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				int bLinear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 				u32 ulOverlayOffset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 				u32 * retStride, u32 * retUVStride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern int SetOverlayBlendMode(volatile STG4000REG __iomem *pSTGReg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			       OVRL_BLEND_MODE mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			       u32 ulAlpha, u32 ulColorKey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern int SetOverlayViewPort(volatile STG4000REG __iomem *pSTGReg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			      u32 left, u32 top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			      u32 right, u32 bottom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern void EnableOverlayPlane(volatile STG4000REG __iomem *pSTGReg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* _STG4000INTERFACE_H */